Packaging information
| Package | Pins VQFN (RHB) | 32 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 3,000 | LARGE T&R |
Features for the TUSB1210-Q1
- AEC-Q100 Qualified with:
- Temperature Grade 3: –40°C to 85°C
- HBM ESD Classification 1C
- CDM ESD Classification C4B
- USB2.0 PHY Transceiver Chip, Designed to Interface
with a USB Controller via a ULPI 12-pin Interface,
Fully Compliant With:- Universal Serial Bus Specification Rev. 2.0
- On-The-Go Supplement to the USB
2.0 Specification Rev. 1.3 - UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1
- DP/DM Line External Component Compensation
(Patent #US7965100 B1) - Interfaces to Host, Peripheral and OTG Device Cores;
Optimized for Portable Devices or System ASICs with
Built-in USB OTG Device Core - Complete USB OTG Physical Front-End that Supports
Host Negotiation Protocol (HNP) and Session Request
Protocol (SRP) - ULPI Interface:
- I/O Interface (1.8 V) Optimized for Non-Terminated
50 Ω Line Impedance - ULPI CLOCK Pin (60 MHz) Supports Both Input
and Output Clock Configurations - Fully Programmable ULPI-Compliant Register Set
- I/O Interface (1.8 V) Optimized for Non-Terminated
- Available in a 32-Pin Quad Flat No Lead
[QFN (RHB)] Package
Description for the TUSB1210-Q1
The TUSB1210-Q1 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI interface. It supports all USB2.0 data rates (High-Speed 480 Mbps, Full-Speed 12 Mbps and Low-Speed 1.5 Mbps), and is compliant to both Host and Peripheral modes. It additionally supports a UART mode and legacy ULPI serial modes.
TUSB1210-Q1 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).
The DP/DM external component compensation in the transmitter compensates for variations in the series impendence in order to match with the data line impedance and the receiver input impedance, to limit data reflections, and thereby, improve eye diagrams.