DS92LV16

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16-Bit-Bus LVDS-Serializer/Deserializer – 25–80 MHz

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Datenblatt

document-pdfAcrobat DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz datasheet (Rev. H) (Englisch)

DS92LV16

AKTIV

Datenblatt

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Produktdetails

Function

SerDes

Protocols

Channel-Link I

Number of transmitters

1

Number of receivers

1

Signaling rate (Mbps)

2560

Input signal

BLVDS, LVDS, LVTTL

Output signal

BLVDS, LVDS, LVTTL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

SerDes

Protocols

Channel-Link I

Number of transmitters

1

Number of receivers

1

Signaling rate (Mbps)

2560

Input signal

BLVDS, LVDS, LVTTL

Output signal

BLVDS, LVDS, LVTTL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

LQFP (PN)

80

196 mm² (14 mm × 14 mm)

25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
Line and Local Loopback Modes
Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
No External Coding Required
Internal PLL, No External PLL Components Required
Single +3.3V Power Supply
Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
±100mV Receiver Input Threshold
Loss of Lock Detection and Reporting Pin
Industrial −40 to +85°C Temperature Range
>2.5kV HBM ESD
Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
Line and Local Loopback Modes
Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
No External Coding Required
Internal PLL, No External PLL Components Required
Single +3.3V Power Supply
Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
±100mV Receiver Input Threshold
Loss of Lock Detection and Reporting Pin
Industrial −40 to +85°C Temperature Range
>2.5kV HBM ESD
Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

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Top-Dokumentation	Typ	Titel	Datum
*	Datenblatt	DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz datasheet (Rev. H)	16.04.2013
	Anwendungshinweis	DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)	29.04.2013
	Anwendungshinweis	DS92LV16 Power Up Reset (Rev. B)	26.04.2013
	Anwendungshinweis	How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A)	26.04.2013
	Anwendungshinweis	External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A)	26.04.2013
	Designleitfaden	DS92LV16 16-bit SerDes Design Guide	29.03.2007
	Whitepaper	Easy-to-Use LVDS Serdes for the Serdes Neophyte	01.09.2001

Design und Entwicklung

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DS92LV16 IBIS Model

SNLM027.ZIP (18 KB) - IBIS-Modell

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
LQFP (PN)	80	Ultra Librarian

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DS92LV16

16-Bit-Bus LVDS-Serializer/Deserializer – 25–80 MHz

DS92LV16

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