SCANSTA111

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Optimierte Produktpalette (EP) – SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG)-Port

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Datenblatt

document-pdfAcrobat SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port datasheet (Rev. K) (Englisch)

SCANSTA111

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-40 to 85

NFBGA (NZA)

49

49 mm² (7 mm × 7 mm)

TSSOP (DGG)

48

101.25 mm² (12.5 mm × 8.1 mm)

True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
The 7 Slot Inputs Support Up to 121 Unique Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
3 IEEE 1149.1-Compatible Configurable Local Scan Ports
Mode Register₀ Allows Local TAPs to be Bypassed, Selected for Insertion Into the Scan Chain Individually, or Serially in Groups of Two or Three
Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to those on a Single Local Scan Port
LSP ACTIVE Outputs Provide Local Port Enable Signals for Analog Busses Supporting IEEE 1149.4.
General Purpose Local Port Pass-Through Bits are Useful for Delivering Write Pulses for FPGA Programming or Monitoring Device Status.
Known Power-Up State
TRST on All Local Scan Ports
32-Bit TCK Counter
16-Bit LFSR Signature Compactor
Local TAPs can become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP_0-2 Have a TRI-STATE Notification Output)
3.0-3.6V V_CC Supply Operation
Power-Off High Impedance Inputs and Outputs
Supports Live Insertion/Withdrawal

All trademarks are the property of their respective owners.

True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
The 7 Slot Inputs Support Up to 121 Unique Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
3 IEEE 1149.1-Compatible Configurable Local Scan Ports
Mode Register₀ Allows Local TAPs to be Bypassed, Selected for Insertion Into the Scan Chain Individually, or Serially in Groups of Two or Three
Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to those on a Single Local Scan Port
LSP ACTIVE Outputs Provide Local Port Enable Signals for Analog Busses Supporting IEEE 1149.4.
General Purpose Local Port Pass-Through Bits are Useful for Delivering Write Pulses for FPGA Programming or Monitoring Device Status.
Known Power-Up State
TRST on All Local Scan Ports
32-Bit TCK Counter
16-Bit LFSR Signature Compactor
Local TAPs can become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP_0-2 Have a TRI-STATE Notification Output)
3.0-3.6V V_CC Supply Operation
Power-Off High Impedance Inputs and Outputs
Supports Live Insertion/Withdrawal

All trademarks are the property of their respective owners.

The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE 1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Datum
*	Datenblatt	SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port datasheet (Rev. K)	12.04.2013
	Anwendungshinweis	Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D)	26.04.2013
	Anwendungshinweis	AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B)	26.04.2013
	Anwendungshinweis	AN-1259 SCANSTA112 Designer's Reference (Rev. H)	26.04.2013
	Anwendungshinweis	Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C)	26.04.2013
	Anwendungshinweis	JTAG Advanced Capabilities and System Design	19.03.2009
	Anwendungshinweis	Partition IEEE 1149.1 SCAN Chains for Manageability!	06.03.2003

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Support-Software

EVF-WORKBENCH-CONVERTER-SW — EVF Workbench - Converts JTAG SVF to National’s EVF2 SCAN Format

Graphical User Interface tool for conversion of SVF files to Texas Instrument’s EVF2 embedded file format. Zip file includes readme file, license file, and setup program (1.6MB)

Unterstützte Produkte und Hardware

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