Startseite Schnittstelle LVDS-, M-LVDS- und PECL-ICs
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LVDS-, M-LVDS- und PECL-ICs

SN65MLVD3

AKTIV

1-Kanal-M-LVDS Typ-2 Empfänger

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Datenblatt

SN65MLVD3

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Function Receiver Protocols M-LVDS Number of transmitters 0 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 250 Input signal M-LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols M-LVDS Number of transmitters 0 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 250 Input signal M-LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
VSON (DRB) 8 9 mm² 3 x 3
  • Low-Voltage Differential 30- Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz
  • SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
  • SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions
  • Wide Receiver Input Common-Mode Voltage Range, -1 V to 3.4 V, Allows 2 V of Ground Noise
  • Improved VIT (35 mV)
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology
  • High Input Impedance with Low Supply Voltage
  • Bus-Pin HBM ESD Protection Exceeds 9 kV
  • Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC
  • APPLICATIONS
    • Parallel Multipoint Data and Clock Transmission via Backplanes and Cables
    • Cellular Base Stations
    • Central Office Switches
    • Network Switches and Routers

(1) The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).
  • Low-Voltage Differential 30- Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz
  • SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
  • SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions
  • Wide Receiver Input Common-Mode Voltage Range, -1 V to 3.4 V, Allows 2 V of Ground Noise
  • Improved VIT (35 mV)
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology
  • High Input Impedance with Low Supply Voltage
  • Bus-Pin HBM ESD Protection Exceeds 9 kV
  • Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC
  • APPLICATIONS
    • Parallel Multipoint Data and Clock Transmission via Backplanes and Cables
    • Cellular Base Stations
    • Central Office Switches
    • Network Switches and Routers

(1) The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.

The devices are characterized for operation from -40°C to 85°C.

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.

The devices are characterized for operation from -40°C to 85°C.
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Technische Dokumentation

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Alle anzeigen 5
Typ Titel Datum
* Data sheet Single M-LVDS Receivers datasheet 02 Nov 2006
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) PDF | HTML 22 Jun 2023
Application brief How Far, How Fast Can You Operate MLVDS? 06 Aug 2018
EVM User's guide Mulitpoint-Low Voltage Differential Sgnaling (M-LVDS) EVM 29 Jun 2007
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 20 Nov 2001

Design und Entwicklung

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Evaluierungsplatine

SN65MLVD2-3EVM — SN65MLVD2-3EVM-Evaluierungsmodul

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low, (...)

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SN65MLVD2 IBIS Model

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SN65MLVD3 IBIS Model

SLLC290.ZIP (12 KB) - IBIS Model
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PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese voll ausgestattete Design- und Simulationssuite verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Bestellen & Qualität

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