Home Interface Other interfaces
Home
Interface
Other interfaces

DS99R104

ACTIVE

3-MHz to 40-MHz DC-balanced 24-bit LVDS deserializer for -40C to 85C

Order now
Data sheet

DS99R104

ACTIVE
Data sheet Order now

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TQFP (PFB) 48 81 mm² 9 x 9 WQFN (NJU) 48 49 mm² 7 x 7
  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
filter Find other Other interfaces
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 5
Type Title Date
* Data sheet DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet (Rev. D) 16 Apr 2013
Application note LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) 29 Apr 2013
Application note Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) 26 Apr 2013
User guide SERDES Demonstration Kit User Manual 25 Jan 2012
Design guide Channel Link II Design Guide 21 Jan 2011

Design & development

Please view the Design & development section on a desktop.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos