ADC12J4000

The ADC12J4000EVM is an evaluation module (EVM) that allows for the evaluation of TI's ADC12J4000. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and decimation (...)

La IP de diseño rápido JESD204 se diseñó para permitir a los ingenieros de FPGA lograr una ruta acelerada hacia un sistema JESD204 en funcionamiento. La IP se diseñó de manera que el procesamiento digital descendente y otras lógicas de aplicación estén aislados de la mayoría de las restricciones (...)

Esta interfaz gráfica de usuario (GUI) de convertidor de datos de alta velocidad pro es un programa para PC (compatible con Windows® XP/7/10) que está diseñado para ayudar en la evaluación de la mayoría de los convertidores de datos de alta velocidad (convertidor de señal analógica a digital [ADC] (...)

Esta calculadora Excel proporciona a los diseñadores de sistemas una forma de simplificar el diseño y la depuración de receptores de muestreo de RF directo. Ofrece tres funciones: planificación de frecuencias, filtrado analógico y localización de espurios del filtro de decimación.

En la fase de (...)

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)

Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)

A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual (...)

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.

For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)