TPS53317

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Convertidor SWIFT™ sincrónico reductor 6 A y baja tensión de entrada para terminación de memoria DDR

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document-pdfAcrobat TPS53317 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination datasheet (Rev. D) (Inglés) PDF | HTML

TPS53317

ACTIVO

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Detalles del producto

Product type

DDR

Vin (min) (V)

1

Vin (max) (V)

6

Vout (min) (V)

-0.3

Vout (max) (V)

3.6

Features

Complete Solution

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Iq (typ) (mA)

0.32

DDR memory type

DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3

Product type

DDR

Vin (min) (V)

1

Vin (max) (V)

6

Vout (min) (V)

-0.3

Vout (max) (V)

3.6

Features

Complete Solution

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Iq (typ) (mA)

0.32

DDR memory type

DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3

VQFN (RGB)

20

14 mm² (4 mm × 3.5 mm)

TI proprietary Integrated MOSFET and Packaging Technology
Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
External Tracking
Minimum External Components Count
to 6-V Conversion Voltage
D-CAP+ Mode Architecture
Supports All MLCC Output Capacitors and SP/POSCAP
Selectable SKIP Mode or Forced CCM
Optimized Efficiency at Light and Heavy Loads
Selectable 600-kHz or 1-MHz Switching Frequency
Selectable Overcurrent Limit (OCL)
Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
Adjustable Output Voltage from to 2 V
3.5 mm × 4 mm, 20-Pin VQFN Package

TI proprietary Integrated MOSFET and Packaging Technology
Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
External Tracking
Minimum External Components Count
to 6-V Conversion Voltage
D-CAP+ Mode Architecture
Supports All MLCC Output Capacitors and SP/POSCAP
Selectable SKIP Mode or Forced CCM
Optimized Efficiency at Light and Heavy Loads
Selectable 600-kHz or 1-MHz Switching Frequency
Selectable Overcurrent Limit (OCL)
Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
Adjustable Output Voltage from to 2 V
3.5 mm × 4 mm, 20-Pin VQFN Package

The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ V_DDQ with both sink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device can also be used for other point-of-load (POL) regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, output sinking current capability with tight voltage regulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrated droop support, external tracking capability, pre-bias startup, output soft discharge, integrated bootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic and SP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.

The device is available in the 3.5 mm × 4 mm, 20-pin, VQFN package (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

For all available packages, see the orderable addendum at the end of the data sheet.

The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ V_DDQ with both sink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device can also be used for other point-of-load (POL) regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, output sinking current capability with tight voltage regulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrated droop support, external tracking capability, pre-bias startup, output soft discharge, integrated bootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic and SP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.

The device is available in the 3.5 mm × 4 mm, 20-pin, VQFN package (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

For all available packages, see the orderable addendum at the end of the data sheet.

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Documentación principal	Tipo	Título	Opciones de formato	Fecha
*	Hoja de datos	TPS53317 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination datasheet (Rev. D)	PDF \| HTML	10/07/2015
	Guía de selección	SWIFT DC/DC Converters Selector Guide (Rev. G)		6/02/2019
	Guía de selección	Power Management Guide 2018 (Rev. R)		25/06/2018

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