홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 멀티미디어 및 산업용 네트워킹 SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
멀티미디어 및 산업용 네트워킹 SoC

AM3359

활성

Sitara 프로세서: Arm Cortex-A8, EtherCAT, 3D, PRU-ICSS, CAN

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데이터 시트

AM3359

활성
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제품 상세 정보

CPU 1 Arm Cortex-A8 Frequency (MHz) 800 Graphics acceleration 1 3D Display type 1 LCD Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 800 Graphics acceleration 1 3D Display type 1 LCD Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105
NFBGA (ZCZ) 324 225 mm² (15 mm × 15 mm)
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
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* 데이터 시트 AM335x Sitara™ Processors datasheet (Rev. L) PDF | HTML 2019. 11. 15
* 정오표 AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) 2017. 1. 3
백서 TI Sitara™ 프로세서의 PROFINET® PDF | HTML 2026. 4. 17
애플리케이션 노트 Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2026. 2. 12
애플리케이션 노트 HSR/PRP Solutions on Sitara Processors for Grid Substation Communication (Rev. A) PDF | HTML 2026. 1. 30
애플리케이션 노트 Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025. 11. 24
애플리케이션 노트 Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 2025. 9. 3
애플리케이션 노트 AM335x Power Estimation Tool (Rev. A) PDF | HTML 2025. 6. 11
백서 Securing Arm-Based Application Processors (Rev. F) PDF | HTML 2025. 2. 26
애플리케이션 노트 Basic Ethernet Interface Debug With Linux PDF | HTML 2024. 10. 11
백서 Time Sensitive Networking for Industrial Automation (Rev. C) PDF | HTML 2023. 7. 31
애플리케이션 노트 Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023. 5. 24
애플리케이션 노트 High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023. 2. 24
애플리케이션 노트 PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022. 10. 11
설계 가이드 Discrete Power Solution for AM335x in 12mmx12mm Form-Factor Reference Design (Rev. A) PDF | HTML 2021. 11. 9
애플리케이션 노트 nfBGA Packaging (Rev. C) PDF | HTML 2021. 5. 17
애플리케이션 노트 Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) 2021. 5. 7
추가 자료 From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020. 12. 16
백서 EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020. 7. 28
백서 EtherCAT® on Sitara™ Processors (Rev. I) 2020. 7. 28
사용 설명서 Powering the AM335x, AM437x, and AM438x with TPS65218D0 (Rev. B) 2020. 2. 27
애플리케이션 노트 AM335x Schematic Checklist (Rev. A) PDF | HTML 2019. 12. 19
사용 설명서 AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 2019. 12. 13
애플리케이션 노트 AM335x EMIF Tools 2019. 9. 20
애플리케이션 노트 AM335x PMIC Selection Guide (Rev. A) 2019. 9. 19
애플리케이션 노트 Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 2019. 9. 13
Product overview Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) 2019. 7. 30
백서 Power optimization techniques for energy-efficient systems (Rev. A) 2019. 6. 28
애플리케이션 노트 Calculating Useful Lifetimes of Embedded Processors (Rev. B) PDF | HTML 2019. 5. 7
애플리케이션 노트 AM335x Hardware Design Guide PDF | HTML 2019. 5. 3
애플리케이션 노트 How to Port WOLFSSL Onto TI Sitara AM335 Starter Kit PDF | HTML 2019. 4. 24
사용 설명서 Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 PDF | HTML 2019. 4. 11
애플리케이션 노트 Common EOS pitfalls in board design PDF | HTML 2019. 2. 13
애플리케이션 노트 PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 2019. 1. 18
애플리케이션 노트 McASP Design Guide - Tips, Tricks, and Practical Examples 2019. 1. 10
애플리케이션 노트 PRU Read Latencies (Rev. A) 2018. 12. 21
애플리케이션 노트 PRU-ICSS Getting Starting Guide on Linux (Rev. A) PDF | HTML 2018. 12. 10
백서 Ensuring real-time predictability (Rev. B) 2018. 12. 4
애플리케이션 노트 PRU-ICSS EtherCAT Slave Troubleshooting Guide 2018. 11. 7
애플리케이션 노트 PRU-ICSS / PRU_ICSSG Migration Guide PDF | HTML 2018. 11. 5
백서 Secure Boot on embedded Sitara™ processors (Rev. A) 2018. 10. 13
사용 설명서 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018. 9. 24
백서 An inside look at industrial Ethernet communication protocols (Rev. B) 2018. 8. 1
애플리케이션 노트 Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) 2018. 3. 28
사용 설명서 Powering the AM335x With the TPS650250 (Rev. B) 2018. 3. 14
백서 Data concentrators: The core of energy and data management (Rev. A) 2018. 2. 21
사용 설명서 PRU Assembly Instruction User Guide 2018. 2. 16
백서 POWERLINK on TI Sitara Processors (Rev. A) 2018. 1. 10
Product overview TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) 2017. 12. 19
사용 설명서 TPS65910Ax User's Guide for AM335x Processors (Rev. F) 2017. 12. 8
사용 설명서 Sub-1 GHz Sensor-to-Cloud Linux® E14 Kit 2017. 10. 16
기술 문서 New industrial Ethernet protocol: CC-Link IE Field Basic PDF | HTML 2017. 9. 29
애플리케이션 노트 Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017. 8. 14
애플리케이션 노트 Processor-SDK RTOS Power Management and Measurement 2017. 8. 2
애플리케이션 노트 Sitara Linux ALSA DSP Microphone Array Voice Recognition 2017. 6. 30
백서 Connected sensors in industrial automation (Rev. B) 2017. 6. 22
애플리케이션 노트 AM335x Reliability Considerations in PLC Applications (Rev. A) 2017. 4. 27
애플리케이션 노트 AM335x Low Power Design Guide (Rev. A) 2017. 2. 28
백서 Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 2016. 8. 11
기술 문서 How to select the right industrial Ethernet standard: Do you speak multiprotocol? PDF | HTML 2016. 7. 28
설계 가이드 EtherCAT Master Stack for TI Sitara CPU Family Design Guide (Rev. A) 2016. 7. 19
기술 문서 How to select the right industrial Ethernet standard: Ethernet POWERLINK PDF | HTML 2016. 5. 9
설계 가이드 Parallel Redundancy Protocol Ethernet for Substation Automation Design Guide 2016. 3. 29
기술 문서 How to select the right industrial Ethernet standard: EtherNet/IP PDF | HTML 2016. 2. 25
Product overview Sitara™ AM5x processor with ARM® Cortex™-A15 core (Rev. A) 2016. 1. 22
백서 Building automation for enhanced energy and operational efficiency (Rev. A) 2015. 10. 26
기술 문서 How to select the right industrial Ethernet standard: EtherCAT PDF | HTML 2015. 9. 17
애플리케이션 노트 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015. 8. 13
기술 문서 How to select the right industrial Ethernet standard: Sercos III PDF | HTML 2015. 7. 23
백서 Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) 2015. 3. 3
사용 설명서 G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide 2014. 11. 13
사용 설명서 Powering the AM335x with the TPS65217x . (Rev. I) 2014. 9. 6
백서 Mainline Linux™ ensures stability and innovation 2014. 3. 27
백서 Scalable Solutions for HMI 2013. 11. 21
백서 Linaro Speeds Development in TI Linux SDKs PDF | HTML 2013. 8. 27
백서 The Yocto Project:Changing the way embedded Linux software solutions are develop 2013. 3. 14
백서 Smart thermostats are a cool addition to the connected home 2012. 9. 27

설계 및 개발

전원 공급 솔루션

AM3359에 사용 가능한 전원 공급 솔루션을 찾아보세요. TI는 칩(SoC), 프로세서, 마이크로컨트롤러, 센서 또는 FPGA(Field Programmable Gate Array)의 TI와 비TI 시스템을 위한 전원 공급 솔루션을 제공합니다.

솔루션 보기
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TMDSICE3359 — AM3359 산업용 통신 엔진

The AM3359 Industrial Communications Engine (ICE) is a development platform targeted for systems that specifically focus on the industrial communications capabilities of the Sitara AM335x Arm® Cortex™-A8 processors.

The AM335x Arm Cortex-A8 processors integrate the Programmable Real-time Unit (PRU) (...)

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TMDXEVM3358 — AM335x 평가 모듈

The AM335x Evaluation Module (EVM) enables developers to immediately start evaluating the AM335x processor family (AM3351, AM3352, AM3354, AM3356, AM3358) and begin building applications for factory automation, building automation, grid infrastructure, and more.

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TPS65217CEVM — TPS65217C 평가 모듈

The TPS65217CEVM is a fully assembled platform for evaluating the performance of the TPS65217C power management device.

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TPS65218EVM-100 — TPS65218 평가 모듈

The TPS65218EVM is a fully assembled platform for evaluating the performance of the TPS65218 power management device.

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ADVAN-3P-SITARA-SOMS — Advantech Sitara SOM 및 SBC

Advantech offers Sitara™ based embedded core computing solutions including computer-on-modules, single-board-computers and box computers. Their compact, low-power-consumption, and cost-effective Arm®-based platform solutions are designed to deliver easier system integration, better (...)
발송: Advantech
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BYTES-3P-SITARASOMS — bytes at work Sitara SOM

bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


발송: bytes at work AG
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COMPU-3P-SITARASOMS — Compulab Sitara SOM

CompuLab is a leading manufacturer of computer-on-module boards and miniature PC systems. CompuLab's products excel with an advanced set of features, outstanding level of integration, high reliability and affordable prices. Annual manufacturing rate of over 100,000 boards and systems positions (...)
발송: CompuLab
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CRLNK-3P-SOMS — Critical Link system on modules for TI ARM-based Processors

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

발송: Critical Link LLC
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FORLX-3P-SITARA-SOMS — Forlinx Sitara SOM

As a member unit of CSIA (China Software Industry Association) Embedded System Branch, Forlinx Embedded Tech Co., Ltd. has the capability to design, prototype and manufacture printed circuit boards, sub-assemblies and complete electronic products. Forlinx is committed to the development of Sitara (...)
발송: Forlinx Embedded Tech. Co., Ltd
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MYIR-3P-SITARASOMS — MYIR Sitara SOM

MYIR offers a series of development kits and system-on-modules based on TI's AM335x Arm® Cortex®-A8 processors to meet customers' different requirements. MYIR also offers a compact single board computer Rico board based on TI's newest AM437x Arm Cortex-A9 solution. MYIR also offers custom (...)
발송: MYIR Tech Limited
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OCTVO-3P-AM335X — Octavo 시스템 AM335x 기반 시스템-인-패키지

Octavo Systems는 전 세계의 혁신가에게 SIP(System-in-Package) 기반 솔루션을 제공하는 선도 기업입니다. SIP 장치로 구성된 OSD335x 제품군은 텍사스 인스트루먼트의 Sitara™ AM335x Arm® Cortex®-A8 프로세서 기반의 고성능 임베디드 시스템을 개발하고 배포할 수 있는 가장 빠르고 경제적인 방법입니다.

OSD335x 장치는 최대 1GHz로 실행되는 Sitara™ AM335x Arm® Cortex®-A8 프로세서와 최대 1GB의 DDR3, TPS65217C 전력 관리 IC, (...)

발송: Octavo Systems
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PHYTC-3P-PHYBOARD-AM335X — AM335x Arm® 기반 Sitara™ 프로세서용 PHYTEC® phyBOARD® -AM335x 개발 키트

phyBOARD®-AM335x는 캐리어 보드 PCB에 직접 납땜되는 TI Sitara™ AM335x를 기반으로 하는 phyCORE-AM335x SOM(System On Module)을 갖추고 있습니다. 캐리어 보드에 대한 SOM의 이 "DSC(직접 납땜 연결)" 방식은 보드 간 커넥터를 제거하여 시스템 비용을 줄입니다. Pico-ITX 폼 팩터에서 phyBOARD는 광범위한 강력한 산업 응용 제품에 배포하는 데 이상적입니다.

PHYTEC는 고객이 복잡한 제품을 빠르고 쉽게 시장에 출시할 수 있도록 지원하는 SOM(System on (...)

발송: PHYTEC
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TQ-3P-SITARASOMS — TQ Group Sitara SOM

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
발송: TQ-Group
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VANWS-3P-VGATEWAY — AM335x 기반 Vanteon Wireless Solutions의 vGATEWAY 레퍼런스 설계

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

발송: Vanteon Wireless Solutions
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VAR-3P-SITARASOMS — Variscite Sitara SOM

Variscite designs and produces a variety of system on modules and single board computers based TI's Sitara™, OMAP™ and DaVinci™ processors, covering a wide range of products, segments and markets. Variscite provides its customers with a complete development kit supporting Windows (...)
발송: Variscite
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도터 카드

PRUCAPE — TI PRU 케이프

The TI PRU Cape is a BeagleBone Black add-on board that allows users get to know TI’s powerful Programmable Real-Time Unit (PRU) core and basic functionality. The PRU is a low-latency microcontroller subsystem integrated in the Sitara AM335x and AM437x family of devices.  The PRU core is (...)

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WL1835MODCOM8B — WiLink™ 8 모듈 2.4GHz Wi-Fi® + Bluetooth® COM8 평가 모듈

TI WiLink™ 8 module family

The WL1835MODCOM8 is one of the two evaluation boards for the TI WiLink 8 combo module family. For designs requiring performance in the 5 GHz band and extended temperature range, see the WL1837MODCOM8I.

The WL1835MODCOM8 Kit for Sitara EVMs easily enables customers to add (...)

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WL1837MODCOM8I — WiLink™ 8 듀얼 밴드 2.4 및 5GHz Wi-Fi® + Bluetooth® COM8 평가 모듈

TI WiLink™ 8 module family The WL1837MODCOM8I is one of the two evaluation boards for the TI WiLink™ 8 combo module family. For designs requiring performance in the 2.4 GHz band only, see the WL1835MODCOM8.

The WL1837MODCOM8I, which is compatible with many processors including TI’s (...)

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디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 장치를 디버깅하는 데 사용되는 디버그 프로브(에뮬레이터)입니다. 대부분의 장치의 경우 더욱 저렴한 신형 XDS110(www.ti.com/tool/TMDSEMU110-U)을 사용하실 것을 권장합니다. XDS200은 단일 포드에서 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(임베디드 트레이스 버퍼)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 트레이스를 지원합니다.

XDS200은 TI 20핀 커넥터(TI 14핀, (...)

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TMDSEMU560V2STM-U — XDS560™ 소프트웨어 v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다.  SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(임베디드 추적 버퍼)가 있는 모든 ARM 및 DSP 프로세서에서 코어와 시스템 트레이스를 지원합니다.  핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, TI 20핀 및 ARM (...)

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TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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LB-3P-TRACE32-ARM — Arm® 기반 마이크로컨트롤러 및 프로세서용 Lauterbach TRACE32® 디버그 및 트레이스 시스템

Lauterbach의 TRACE32® 툴은 개발자가 모든 종류의 Arm® 기반 마이크로컨트롤러 및 프로세서를 분석, 최적화 및 인증할 수 있도록 하는 첨단 하드웨어 및 소프트웨어 구성 요소 제품군입니다. 세계적으로 유명한 임베디드 시스템 및 SoC용 디버그 및 트레이스 솔루션은 초기 사전 실리콘 개발부터 현장의 제품 인증 및 문제 해결에 이르기까지 모든 개발 단계를 위한 완벽한 솔루션입니다. Lauterbach 툴의 직관적인 모듈형 설계는 엔지니어에게 현존하는 최고의 성능을 제공하고 요구 사항 변화에 따라 적응하고 성장하는 (...)

발송: Lauterbach GmbH
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소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-AM335X — Linux Processor SDK for AM335x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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PROCESSOR-SDK-LINUX-RT-AM335X — Linux-RT Processor SDK for AM335x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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PROCESSOR-SDK-RTOS-AM335X — TI-RTOS Processor SDK for AM335x and AMIC110 devices (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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소프트웨어 개발 키트(SDK)

TIBLUETOOTHSTACK-SDK — TI 이중 모드 블루투스® 스택

TI의 이중 모드 블루투스 스택은 블루투스 + Bluetooth 저에너지를 지원하며 블루투스 4.0/4.1/4.2 사양을 구현하는 단일 모드 및 이중 모드 제품으로 구성되어 있습니다. 블루투스 스택은 Bluetooth SIG(Special Interest Group)의 완전한 검증을 거쳤으며 인증을 받았고 로열티가 없으며 개발 속도를 높이는 간단한 명령줄 샘플 애플리케이션을 제공하고 요청 시 MFI 기능을 제공합니다.

스택은 다음 장치에서 작동합니다:

지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

지원되는 제품 및 하드웨어
IDE, 구성, 컴파일러 또는 디버거

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

지원되는 제품 및 하드웨어
운영 체제(OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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운영 체제(OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
발송: Mentor Graphics Corporation
지원되는 제품 및 하드웨어
운영 체제(OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® RTOS(실시간 운영 체제)는 자동차, 의료, 운송, 군사 및 산업용 임베디드 시스템을 위한 차세대 제품을 지원하도록 설계된 모든 기능을 갖춘 견고한 RTOS입니다. 마이크로커널 설계 및 모듈식 아키텍처를 통해 고객은 낮은 총 소유 비용으로 고도로 최적화되고 안정적인 시스템을 만들 수 있습니다.
발송: QNX
지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

PRU-ICSS-ETHERCAT-SLAVE — PRU-ICSS software for EtherCAT slave

PRU-ICSS 프로토콜은 TI Sitara 프로세서를 위한 실시간 산업용 통신을 지원합니다.  PRU-ICSS 프로토콜은 TI의 통합 소프트웨어 개발 플랫폼인 Processor-SDK-RTOS를 기반으로 사용하도록 구축되었으며 최적화된 PRU-ICSS 펌웨어, ARM 프로세서에 해당하는 PRU-ICSS 드라이버 및 예제 애플리케이션을 포함하고 있습니다. PRU-ICSS 펌웨어는 PRU 코어에서 실행되며 기본 ARM 프로세서에서 시간이 중요한 링크 계층 프로세싱을 오프로드하고 TI-RTOS를 실행합니다. PRU-ICSS 드라이버는 (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

PRU-ICSS-ETHERNETIP-ADAPTER — PRU-ICSS software for EtherNetIP adapter

PRU-ICSS 프로토콜은 TI Sitara 프로세서를 위한 실시간 산업용 통신을 지원합니다.  PRU-ICSS 프로토콜은 TI의 통합 소프트웨어 개발 플랫폼인 Processor-SDK-RTOS를 기반으로 사용하도록 구축되었으며 최적화된 PRU-ICSS 펌웨어, ARM 프로세서에 해당하는 PRU-ICSS 드라이버 및 예제 애플리케이션을 포함하고 있습니다. PRU-ICSS 펌웨어는 PRU 코어에서 실행되며 기본 ARM 프로세서에서 시간이 중요한 링크 계층 프로세싱을 오프로드하고 TI-RTOS를 실행합니다. PRU-ICSS 드라이버는 (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

PRU-ICSS-HSR-PRP-DAN — PRU-ICSS software for HSR/PRP

PRU-ICSS 프로토콜은 TI Sitara 프로세서를 위한 실시간 산업용 통신을 지원합니다.  PRU-ICSS 프로토콜은 TI의 통합 소프트웨어 개발 플랫폼인 Processor-SDK-RTOS를 기반으로 사용하도록 구축되었으며 최적화된 PRU-ICSS 펌웨어, ARM 프로세서에 해당하는 PRU-ICSS 드라이버 및 예제 애플리케이션을 포함하고 있습니다. PRU-ICSS 펌웨어는 PRU 코어에서 실행되며 기본 ARM 프로세서에서 시간이 중요한 링크 계층 프로세싱을 오프로드하고 TI-RTOS를 실행합니다. PRU-ICSS 드라이버는 (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

PRU-ICSS-PROFIBUS-SLAVE — PRU-ICSS software for PROFIBUS slave

PRU-ICSS 프로토콜은 TI Sitara 프로세서를 위한 실시간 산업용 통신을 지원합니다.  PRU-ICSS 프로토콜은 TI의 통합 소프트웨어 개발 플랫폼인 Processor-SDK-RTOS를 기반으로 사용하도록 구축되었으며 최적화된 PRU-ICSS 펌웨어, ARM 프로세서에 해당하는 PRU-ICSS 드라이버 및 예제 애플리케이션을 포함하고 있습니다. PRU-ICSS 펌웨어는 PRU 코어에서 실행되며 기본 ARM 프로세서에서 시간이 중요한 링크 계층 프로세싱을 오프로드하고 TI-RTOS를 실행합니다. PRU-ICSS 드라이버는 (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

PRU-ICSS-PROFINET-SLAVE — PRU-ICSS software for Profinet slave

PRU-ICSS 프로토콜은 TI Sitara 프로세서를 위한 실시간 산업용 통신을 지원합니다.  PRU-ICSS 프로토콜은 TI의 통합 소프트웨어 개발 플랫폼인 Processor-SDK-RTOS를 기반으로 사용하도록 구축되었으며 최적화된 PRU-ICSS 펌웨어, ARM 프로세서에 해당하는 PRU-ICSS 드라이버 및 예제 애플리케이션을 포함하고 있습니다. PRU-ICSS 펌웨어는 PRU 코어에서 실행되며 기본 ARM 프로세서에서 시간이 중요한 링크 계층 프로세싱을 오프로드하고 TI-RTOS를 실행합니다. PRU-ICSS 드라이버는 (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

TI-15.4-STACK-GATEWAY-LINUX-SDK — TI 15.4-Stack 게이트웨이 Linux 소프트웨어 개발 키트

The TI-15.4-Stack-Gateway-Linux Software Development Kit (SDK) provides a Linux software middleware for the TI 15.4-Stack companion solution. It includes a full Linux user-space software that runs on top of the TI Processor SDK for AM335x platform, which interfaces with the co-processor embedded (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

WIND-3P-VXWORKS-LINUX-OS — Wind River 프로세서 VxWorks 및 Linux 운영 체제

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)

발송: Wind River Systems
지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

WIT-3P-SITARABSP — Witekio Sitara Android 및 Windows 운영 체제

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
발송: Witekio
지원되는 제품 및 하드웨어
펌웨어

TIDCA07 — TIDA-00204 Demo Firmware for AM3359 DP83867 Gigabit Ethernet

지원되는 제품 및 하드웨어
소프트웨어 프로그래밍 도구

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

Sitara™ EMIF 툴은 외부 DDR 메모리 장치에 액세스하기 위해 TI 프로세서를 구성하는 인터페이스를 제공하는 소프트웨어 툴입니다. 또한 이 툴은 보드 라우팅 스큐를 보상하도록 DLL(Delay Locked Loop) 설정을 최적화합니다. 결과는 EMIF 구성 레지스터로 출력되며, 이를 가져와서 프로세서 SDK, Code Composer Studio 또는 사용자 지정 소프트웨어에서 사용할 수 있습니다.  

지원되는 제품 및 하드웨어
소프트웨어 프로그래밍 도구

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash는 TI의 광범위한 CCStudio™ 개발 에코시스템의 일부로, TI 마이크로컨트롤러 및 무선 연결 장치의 온칩 플래시와 TI 프로세서의 온보드 플래시를 프로그래밍하기 위한 소프트웨어 도구입니다. UniFlash는 그래픽 및 명령줄 인터페이스를 모두 제공하며, 데스크톱 또는 클라우드 환경에서 실행할 수 있습니다.

UniFlash는 CCStudio™ 개발자 영역의 클라우드에서 실행하거나 Windows®, Linux®, macOS® 컴퓨터에서 다운로드해 사용할 수 있습니다.

macOS는 mmWave, AMx, K2G 및 (...)

지원되는 제품 및 하드웨어
지원 소프트웨어

AUTOMATA-3P-INDUSTRIALCOMMS — Cannon Automata Sercos III

The Sercos III Slave Communiction Stack allows to implement the Real-time Ethernet protocol Sercos III for any kind of slave devices. The source code includes SCP (Sercos Communication Profile) and GDP (General Device Profile). In addition, the stack already includes many optional function classes (...)
발송: AUTOMATA
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM335x Thermal Model

SPRM824.ZIP (10 KB) - 열 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM335x ZCE IBIS Model (Rev. B)

SPRM556B.ZIP (21124 KB) - IBIS 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM335x ZCE Rev. 2.0 BSDL Model (Rev. A)

SPRM548A.ZIP (8 KB) - BSDL 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM335x ZCE Rev. 2.1 BSDL Model

SPRM606.ZIP (8 KB) - BSDL 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM335x ZCZ Rev. 2.0 BSDL Model (Rev. A)

SPRM549A.ZIP (8 KB) - BSDL 모델
지원되는 제품 및 하드웨어
시뮬레이션 모델

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL 모델
지원되는 제품 및 하드웨어
계산 툴

AM335-PET-CALC — AM335x Power Estimation Tool

AM335x PET provides power consumption estimates based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision.
지원되는 제품 및 하드웨어
계산 툴

CLOCKTREETOOL — Sitara, 오토모티브, 비전 분석 및 디지털 신호 프로세서용 클록 트리 툴

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
지원되는 제품 및 하드웨어
계산 툴

SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF 툴 스프레드시트

Sitara™ EMIF 툴은 외부 DDR 메모리 장치에 액세스하기 위해 TI 프로세서를 구성하는 인터페이스를 제공하는 소프트웨어 툴입니다. 또한 이 툴은 보드 라우팅 스큐를 보상하도록 DLL(Delay Locked Loop) 설정을 최적화합니다. 결과는 EMIF 구성 레지스터로 출력되며, 이를 가져와서 프로세서 SDK, Code Composer Studio 또는 사용자 지정 소프트웨어에서 사용할 수 있습니다.  

지원되는 제품 및 하드웨어

많은 TI 레퍼런스 설계에는 AM3359이(가) 포함됩니다.

레퍼런스 디자인 선택 툴을 사용하여 애플리케이션 및 매개 변수에 가장 적합한 설계를 검토하고 식별할 수 있습니다.
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
NFBGA (ZCZ) 324 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

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지원 및 교육

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포럼 주제 모두 보기(영문)

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