All trademarks are the property of their respective owners.
The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE 1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port datasheet (Rev. K) | 2013/04/12 | |
| Application note | AN-1259 SCANSTA112 Designer's Reference (Rev. H) | 2013/04/26 | ||
| Application note | AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B) | 2013/04/26 | ||
| Application note | Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C) | 2013/04/26 | ||
| Application note | Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D) | 2013/04/26 | ||
| Application note | JTAG Advanced Capabilities and System Design | 2009/03/19 | ||
| Application note | Partition IEEE 1149.1 SCAN Chains for Manageability! | 2003/03/06 |
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| NFBGA (NZA) | 49 | Ultra Librarian |
| TSSOP (DGG) | 48 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.