產品詳細資料

Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 59.8 ENOB (bit) 9.5 SFDR (dB) 67.4 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 59.8 ENOB (bit) 9.5 SFDR (dB) 67.4 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA (NAA) 376 780.6436 mm² 27.94 x 27.94 CLGA (FVA) 256 780.6436 mm² 27.94 x 27.94
  • Total ionizing dose (TID) to 300 krad(Si)
  • Single event functional interrupt (SEFI) tested
  • Single event latch-up (SEL) > 120 MeV-cm2/mg
  • Cold sparing capable
  • Wide temperature range –55°C to +125°C
  • Power consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)
  • 3-dB Input bandwidth = 3 GHz
  • Low-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK ≤ 800 MHz
  • Auto-sync function for multi-chip systems
  • Time stamp feature to capture external trigger
  • Test patterns at output for system debug
  • 1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputs
  • Single 1.9-V power supply
  • Total ionizing dose (TID) to 300 krad(Si)
  • Single event functional interrupt (SEFI) tested
  • Single event latch-up (SEL) > 120 MeV-cm2/mg
  • Cold sparing capable
  • Wide temperature range –55°C to +125°C
  • Power consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)
  • 3-dB Input bandwidth = 3 GHz
  • Low-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK ≤ 800 MHz
  • Auto-sync function for multi-chip systems
  • Time stamp feature to capture external trigger
  • Test patterns at output for system debug
  • 1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputs
  • Single 1.9-V power supply

The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

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類型 標題 日期
* Data sheet ADC12D1620QML-SP 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 2021年 10月 12日
* SMD ADC12D1620QML-SP SMD ADC12D1620QML-SP SMD 5962-12205 2020年 10月 22日
* Radiation & reliability report ADC12D1600QML-SP/ADC12D1620QML-SP Single-Event Effects (SEE) Radiation Report 2020年 7月 27日
* Radiation & reliability report ADC12D1600CCMLS TID Report 2013年 1月 17日
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012年 5月 4日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022年 11月 17日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
Selection guide TI Space Products (Rev. I) 2022年 3月 3日
Application brief Understanding Op Amp Noise in Audio Circuits PDF | HTML 2021年 6月 14日
User guide TSW12D1620EVM-CVAL User's Guide (Rev. A) 2019年 1月 29日
User guide ADC1xD1x00CVAL Board User’s Guide 2017年 6月 9日

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開發板

TSW12D1620EVM-CVAL — ADC12D1620QML-SP 航太級寬頻接收器評估模組

TSW12D1620EVM-CVAL 是 1.5-GHz 寬頻接收器評估模組 (EVM),其中包括放大器、類比轉數位轉換器 (ADC)、時脈、溫度感測器、微控制器及電源解決方案的陶瓷工程模型。電路板最適合從近 DC 到 1.5 GHz 的 IF/RF 頻率數位化。

類比輸入路徑可選擇將 6.5-GHz LMH5401-SP 做為單端至差動增益區塊,或繞過放大器並以差動訊號驅動 ADC。放大器後則為 12 位元、雙 1.6-GSPS 或單 3.2-GSPS ADC12D1620QML-SP。這些高效能元件皆有必要的電源、微控制器和溫度感測器裝置支援。

TSW12D1620EVM-CVAL (...)

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SBAC235 MSP430FR5969 Firmware

lock = 需要匯出核准 (1 分鐘)
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MSP430FR5969 具 64KB FRAM、2KB SRAM、AES、12 位元 ADC、比較器、DMA、UART/SPI/I2C、定時器的 16 MHz MCU MSP430FR5969-SP 抗輻射混合訊號微控制器
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計

TIDA-070004 — 採用整合式數位輸出溫度感測器的航太級參考設計

This reference design illustrates the fact that several spacecraft projects provide a system health status telemetry that ground personnel monitor in real time. This reference design shows an example using a digital output temperature sensor to acquire temperature data on a sub-system using a (...)
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電路圖: PDF
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CLGA (FVA) 256 檢視選項

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