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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12D1620QML-SP

現行

Radiation-hardened, QML-V, 300krad, 12 bit, dual 1.6GSPS or single 3.2GSPS ADC

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產品規格表

ADC12D1620QML-SP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 59.8 ENOB (Bits) 9.5 SFDR (dB) 67.4 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 59.8 ENOB (Bits) 9.5 SFDR (dB) 67.4 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CLGA (FVA) 256 780.6436 mm² (0 mm × 0 mm) CCGA (NAA) 376 780.6436 mm² (0 mm × 0 mm)
  • Total ionizing dose (TID) to 300 krad(Si)
  • Single event functional interrupt (SEFI) tested
  • Single event latch-up (SEL) > 120 MeV-cm2/mg
  • Cold sparing capable
  • Wide temperature range –55°C to +125°C
  • Power consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)
  • 3-dB Input bandwidth = 3 GHz
  • Low-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK ≤ 800 MHz
  • Auto-sync function for multi-chip systems
  • Time stamp feature to capture external trigger
  • Test patterns at output for system debug
  • 1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputs
  • Single 1.9-V power supply
  • Total ionizing dose (TID) to 300 krad(Si)
  • Single event functional interrupt (SEFI) tested
  • Single event latch-up (SEL) > 120 MeV-cm2/mg
  • Cold sparing capable
  • Wide temperature range –55°C to +125°C
  • Power consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)
  • 3-dB Input bandwidth = 3 GHz
  • Low-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK ≤ 800 MHz
  • Auto-sync function for multi-chip systems
  • Time stamp feature to capture external trigger
  • Test patterns at output for system debug
  • 1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputs
  • Single 1.9-V power supply

The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC12D1620QML-SP 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 2021/10/12
* 輻射及可靠性報告 ADC12D1600QML-SP/ADC12D1620QML-SP Single-Event Effects (SEE) Radiation Report 2020/7/27
* 輻射及可靠性報告 Single Event Effects Characterization of Texas Instruments ADC12D1600CCMLS 2018/6/14
* 輻射及可靠性報告 ADC12D1600CCMLS TID Report 2013/1/17
* 輻射及可靠性報告 Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012/5/4
選擇指南 TI Space Products (Rev. L) 2026/3/27
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025/6/17
應用說明 Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025/6/10
更多文件說明 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025/2/20
應用說明 Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
Application brief Understanding Op Amp Noise in Audio Circuits PDF | HTML 2021/6/14
使用指南 ADC1xD1x00CVAL Board User’s Guide 2017/6/9

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TSW12D1620EVM-CVAL — ADC12D1620QML-SP 評估模組，適用 300-krad、12 位元、雙 1.6-GSPS 或單 3.2-GSPS ADC

TSW12D1620EVM-CVAL 是 1.5 GHz 寬頻接收器評估模組 (EVM) ，其中包括放大器、類比轉數位轉換器 (ADC) 、時脈、溫度感測器、微控制器和電源解決方案的陶瓷工程模型。此電路板最適合將近 DC 的 IF/RF 頻率數位化至 1.5 GHz。

類比輸入路徑可選擇將 6.5 GHz LMH5401-SP 做為單端至差動增益區塊，或繞過放大器並以差動訊號驅動 ADC。該放大器後接 12 位元、雙 1.6-GSPS 或單 3.2-GSPS ADC12D1620QML-SP。這些高效能元件皆有必要的電源、微控制器和溫度感測器裝置支援。

TSW12D1620EVM-CVAL (...)

使用指南: PDF
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韌體

SBAC235 — MSP430FR5969 Firmware

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參考設計

TIDA-070004 — 採用整合式數位輸出溫度感測器的航太級參考設計

此參考設計說明瞭幾個航太器專案提供地面人員即時監測的系統健康狀態遙測的事實。此參考設計展示了使用數位輸出溫度感測器的範例，以使用抗輻射 MSP430FR5969-SP 微控制器 (MCU) 在子系統上取得溫度資料。此系統採用 SPI 架構從屬裝置，使用簡易暫存器讀取 / 寫入通訊協定回應主機對溫度資料的要求。此參考設計包括具有 ADC12D1620QML-SP 的本機溫度感測和遠端二極體溫度感測的 TMP461-SP。此參考設計使用的電路板為 TSW12D1620EVM-CVAL。此方法可用作遠端子系統溫度和健康監控器的起點。
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CLGA (FVA) 256 Ultra Librarian
CCGA (NAA) 376 Ultra Librarian
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