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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC34RF52

現行

四通道、14 位元、1.5-GSPS 低雜訊頻譜密度 (NSD) 射頻取樣 ADC

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產品規格表

ADC34RF52

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 2300 Features High Dynamic Range, High Performance, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2920 SNR (dB) 66.3 ENOB (Bits) 10.4 SFDR (dB) 72 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 2300 Features High Dynamic Range, High Performance, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.1 Power consumption (typ) (mW) 2920 SNR (dB) 66.3 ENOB (Bits) 10.4 SFDR (dB) 72 Operating temperature range (°C) -40 to 85 Input buffer No
VQFNP (RTD) 64 81 mm² (9 mm × 9 mm)
  • 14-Bit, Quad channel 1.5-GSPS ADC
  • Noise spectral density:
    • -153 dBFS/Hz without averaging
    • -156 dBFS/Hz with 2x averaging
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 50 fs
  • Low close-in residual phase noise:
    • -133 dBc/Hz at 10 kHz offset
  • Spectral performance (fIN = 900 MHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 65.2 dBFS
    • SFDR HD2,3: 74 dBc
    • SFDR worst spur: 90 dBFS
  • Input fullscale: 1.0/1.1Vpp (1/1.8 dBm)
  • Full power input bandwidth (-3 dB): 1.6 GHz
  • JESD204B serial data interface
    • Maximum lane rate: 13 Gbps
    • Supports subclass 1 deterministic latency
  • Digital down-converters
    • Up to two DDC per ADC channel
    • Complex output: 4x to 128x decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1 µs
  • Power consumption: 0.73 W/channel (1x AVG)
  • Power supplies: 1.8 V, 1.2 V
  • 14-Bit, Quad channel 1.5-GSPS ADC
  • Noise spectral density:
    • -153 dBFS/Hz without averaging
    • -156 dBFS/Hz with 2x averaging
  • Single core (non-interleaved) ADC architecture
  • Aperture jitter: 50 fs
  • Low close-in residual phase noise:
    • -133 dBc/Hz at 10 kHz offset
  • Spectral performance (fIN = 900 MHz, -4 dBFS):
    • 2x internal averaging
    • SNR: 65.2 dBFS
    • SFDR HD2,3: 74 dBc
    • SFDR worst spur: 90 dBFS
  • Input fullscale: 1.0/1.1Vpp (1/1.8 dBm)
  • Full power input bandwidth (-3 dB): 1.6 GHz
  • JESD204B serial data interface
    • Maximum lane rate: 13 Gbps
    • Supports subclass 1 deterministic latency
  • Digital down-converters
    • Up to two DDC per ADC channel
    • Complex output: 4x to 128x decimation
    • 48-bit NCO phase coherent frequency hopping
    • Fast frequency hopping: < 1 µs
  • Power consumption: 0.73 W/channel (1x AVG)
  • Power supplies: 1.8 V, 1.2 V

The ADC34RF52 is a single core 14-bit, 1.5-GSPS, quad channel analog to digital converter (ADC) that supports RF sampling with input frequencies up to 2.5 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -156 dBFS/Hz.

Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.

The ADC34RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. There are only 2 serdes lanes per ADC channel.

The power efficient ADC architecture consumes 0.73 W/ch at 1.5-GSPS and provides power scaling with lower sampling rates.

The ADC34RF52 is a single core 14-bit, 1.5-GSPS, quad channel analog to digital converter (ADC) that supports RF sampling with input frequencies up to 2.5 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -156 dBFS/Hz.

Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.

The ADC34RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. There are only 2 serdes lanes per ADC channel.

The power efficient ADC architecture consumes 0.73 W/ch at 1.5-GSPS and provides power scaling with lower sampling rates.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC34RF52 Quad Channel 14-bit 1.5-GSPS RF Sampling Data Converter datasheet PDF | HTML 2022/1/14
類比設計期刊 高速轉換器奈奎斯特(Nyquist)孔周圍取樣 PDF | HTML Download English Version PDF | HTML 2025/5/23
應用說明 Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 2025/3/28
應用說明 Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 2025/3/26
類比設計期刊 探索 RF 取樣資料轉換器在測試與測量應用中的快速跳頻 PDF | HTML Download English Version PDF | HTML 2024/9/23
應用說明 Improve SFDR Using Calibration in High-Speed ADCs PDF | HTML 2023/6/19

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開發板

ADC32RF55EVM — 適用於具有低 NSD 的雙通道 14 位元 3GSPS 射頻取樣 ADC 的 ADC32RF55 評估模組

ADC32RF55 評估模組 (EVM) 專為評估 ADC32RF55 系列高速類比轉數位轉換器 (ADC) 所設計。本 EVM 搭載 ADC32RF55 晶片，該晶片為具備 JESD204B 介面的 14 位元、雙通道 3GSPS ADC，可評估該系列所有取樣率裝置。
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開發模組 (EVM) 的 GUI

ADC32RF55EVM-GUI — ADC3xRF5xEVM GUI installer/configuration generator

ADC3xRF5xEVM GUI installer/configuration generator
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VQFNP (RTD) 64 Ultra Librarian
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