ADC34RF55
- 14-Bit, quad channel 3-GSPS ADC
- Max output rate: 1.5-GSPS
- Noise spectral density:
- -156 dBFS/Hz without averaging
- -158 dBFS/Hz with 2x averaging
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 50 fs
- Low close-in residual phase noise:
- -127 dBc/Hz at 10 kHz offset
- Spectral performance (f IN = 0.9 GHz, -4 dBFS):
- 2x internal averaging
- SNR: 62.3 dBFS
- SFDR HD2,3: 63 dBc
- SFDR worst spur: 85 dBFS
- Spectral performance (f IN = 1.8 GHz, -4 dBFS):
- 2x internal averaging
- SNR: 63 dBFS
- SFDR HD2,3: 68 dBc
- SFDR worst spur: 86 dBFS
- Input full scale: 1.1, 1.35 Vpp (2, 3.5 dBm)
- Code error rate (CER): 10 -15
- Full power input bandwidth (-3 dB): 2.75 GHz
- JESD204B serial data interface
- Maximum lane rate: 13 Gbps
- Supports subclass 1 deterministic latency
- Digital down-converters
- Up to two DDC per ADC channel
- Complex output: 4x to 128x decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1 µs
- Power consumption: 1.2 W/channel
- Power supplies: 1.8 V, 1.2 V
The ADC34RF55 is a single core 14-bit, 3-GSPS, quad channel analog to digital converters (ADC) that support RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR), and delivers a noise spectral density of -156 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -158 dBFS/Hz.
Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.
The devices supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13Gbps. There are only 2 serdes lanes per ADC channel. Therefore, in bypass mode, the maximum output data rate supported is 1.5GSPS. When using faster ADC sampling rates on chip, decimation is required.
The power efficient ADC architecture consumes 1.2W/ch and provides power scaling with lower sampling rates.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC34RF55 Quad Channel 14-bit 3-GSPS RF Sampling Data Converter datasheet | PDF | HTML | 2023/11/1 | ||
| 類比設計期刊 | 高速轉換器奈奎斯特(Nyquist)孔周圍取樣 | PDF | HTML | Download English Version | PDF | HTML | 2025/5/23 | |
| 應用說明 | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025/3/28 | |||
| 應用說明 | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025/3/26 | |||
| 類比設計期刊 | 探索 RF 取樣資料轉換器在測試與測量應用中的快速跳頻 | PDF | HTML | Download English Version | PDF | HTML | 2024/9/23 | |
| 應用說明 | Improve SFDR Using Calibration in High-Speed ADCs | PDF | HTML | 2023/6/19 |
設計與開發
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ADC32RF55EVM — 適用於具有低 NSD 的雙通道 14 位元 3GSPS 射頻取樣 ADC 的 ADC32RF55 評估模組
ADC32RF55EVM-GUI — ADC3xRF5xEVM GUI installer/configuration generator
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFNP (RTD) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。