DS90CR485
- Up to 6.384-Gbps Throughput
- 66-MHz to 133-MHz Input Clock Support
- Reduces Cable and Connector Size and Cost
- Pre‐Emphasis Reduces Cable Loading Effects
- DC Balance Reduces ISI Distortion
- 24-Bit Double Edge Inputs
- 3-V Tolerant LVCMOS/LVTTL Inputs
- Low Power, 2.5-V Supply
- Flow-Through Pinout
- 100-Pin TQFP Package
- Conforms With TIA/EIA‐644-A LVDS Standard
The DS90CR485 device serializes the 24 LVCMOS/LVTTL double-edge inputs (48 bits data latched in per clock cycle) onto eight Low Voltage Differential Signaling (LVDS) streams. A phase-locked transmit clock is also in parallel with the data streams over a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and connector size and cost. The double-edge input strobes data on both the rising and falling edges of the clock. This minimizes the pin count required and simplifies PCB routing between the host chip and the serializer.
This chip can help resolve EMI and interconnect size problems for high throughput point-to-point applications.
The DS90CR485 is compatible with the DS90CR486 Channel-Link receiver. The device is also backward-compatible with other Channel-Link receivers such as the DS90CR482 and DS90CR484.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90CR485 133-MHz, 48-Bit Channel Link Serializer (6.384 Gbps) datasheet (Rev. E) | PDF | HTML | 2019/9/10 | ||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 設計指南 | Channel Link I Design Guide | 2007/3/29 | ||||
| 應用說明 | Multi-Drop Channel-Link Operation | 2004/10/4 | ||||
| 白皮書 | The Many Flavors of LVDS | 2002/2/1 | ||||
| 應用說明 | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 1998/10/5 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| QFP (NEZ) | 100 | Ultra Librarian |