SN65LVDM176
- Low-Voltage Differential Driver and Receiver for Half-Duplex Operation
- Designed for Signaling Rates of 400 Mbit/s
- ESD Protection Exceeds 15 kV on Bus Pins
- Operates From a Single 3.3-V Supply
- Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a
50-
Load - Valid Output With as Little as 50 mV Input Voltage Difference
- Propagation Delay Times
- Driver: 1.7 ns Typ
- Receiver: 3.7 ns Typ
- Power Dissipation at 200 MHz
- Driver: 50 mW Typical
- Receiver: 60 mW Typical
- LVTTL Levels Are 5-V Tolerant
- Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V
- Open-Circuit Fail-Safe Receiver
- Surface-Mount Packaging
- D Package (SOIC)
- DGK Package (MSOP)
PowerPAD is a trademark of Texas Instruments.
The SN65LVDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50- load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of less than 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and
distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).
The SN65LVDM176 is characterized for operation from \x9640°C to 85°C.
您可能會感興趣的類似產品
功能相似於所比較的產品。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | High-Speed Differential Line Transceiver datasheet (Rev. D) | 2000/8/3 | |||
| 應用說明 | An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) | PDF | HTML | 2023/6/22 | |||
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018/8/6 | ||||
| 應用說明 | Transmission at 200 Mbps in VME Card Cage Using LVDM (Rev. A) | 2002/1/4 | ||||
| 應用說明 | SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) | 2001/11/20 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。