SN74AHC8541

Name: SN74AHC8541
Brand: TI
SKU: SN74AHC8541
Price: 0.594 USD

現行

SN74AHC8541

立即訂購

產品規格表

document-pdfAcrobat SN74AHC8541 8-BIT INVERTING/NONINVERTING SCHMITT-TRIGGER BUFFERS W/3-STATE OUT datasheet (英文)

SN74AHC8541

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

8

Inputs per channel

1

IOL (max) (mA)

12

IOH (max) (mA)

-12

Input type

Standard CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

8

Inputs per channel

1

IOL (max) (mA)

12

IOH (max) (mA)

-12

Input type

Standard CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-40 to 85

PDIP (N)

20

228.702 mm² 24.33 x 9.4

Operating Range of 2 V to 5.5 V V_CC
8-Bit Inverting/Non-Inverting Outputs
20-Pin Thin Shrink Small-Outline Package
[TSSOP (PW)] and 20-Pin Plastic Dual-In-Line
Package [PDIP (N)]

Operating Range of 2 V to 5.5 V V_CC
8-Bit Inverting/Non-Inverting Outputs
20-Pin Thin Shrink Small-Outline Package
[TSSOP (PW)] and 20-Pin Plastic Dual-In-Line
Package [PDIP (N)]

The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is low, the respective gate passes the data from the D input to its Y output.

The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is low, the respective gate passes the data from the D input to its Y output.

The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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