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UC1707-SP

現行

Radiation-hardened, QML-V, 1.5A/1.5A dual-channel gate driver with 40V VDD and output latch

產品詳細資料

Number of channels 2 Power switch IGBT, MOSFET Peak output current (A) 1.5 Input supply voltage (min) (V) 5 Input supply voltage (max) (V) 40 Features Analog Shutdown with Optional Latch, Thermal shutdown Operating temperature range (°C) -55 to 125 Fall time (ns) 40 Input threshold TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating Space Driver configuration Dual
Number of channels 2 Power switch IGBT, MOSFET Peak output current (A) 1.5 Input supply voltage (min) (V) 5 Input supply voltage (max) (V) 40 Features Analog Shutdown with Optional Latch, Thermal shutdown Operating temperature range (°C) -55 to 125 Fall time (ns) 40 Input threshold TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating Space Driver configuration Dual
CFP (W) 16 69.319 mm² (— mm × — mm) CDIP (J) 16 135.3552 mm² (— mm × — mm) LCCC (FK) 20 79.0321 mm² (— mm × — mm)
  • Rad-Tolerant: 50 kRad (Si) for 5962-
    8761903VEA, 5962-8761903VFA(1)
  • QML-V Qualified, SMD
    (5962-8761901VEA, 5962-8761903VEA,
    5962-8761903VFA, 5962-8761901V2A)
  • Two Independent Drivers
  • 1.5-A Totem Pole Outputs
  • Inverting and Non-Inverting Inputs
  • 40-ns Rise and Fall Into 1000 pF
  • High-Speed, Power MOSFET Compatible
  • Low Cross-Conduction Current Spike
  • Analog Shutdown With Optional Latch
  • Low Quiescent Current
  • 5-V to 40-V Operation
  • Thermal Shutdown Protection
  • 16-Pin Dual-In-Line Package
  • Rad-Tolerant: 50 kRad (Si) for 5962-
    8761903VEA, 5962-8761903VFA(1)
  • QML-V Qualified, SMD
    (5962-8761901VEA, 5962-8761903VEA,
    5962-8761903VFA, 5962-8761901V2A)
  • Two Independent Drivers
  • 1.5-A Totem Pole Outputs
  • Inverting and Non-Inverting Inputs
  • 40-ns Rise and Fall Into 1000 pF
  • High-Speed, Power MOSFET Compatible
  • Low Cross-Conduction Current Spike
  • Analog Shutdown With Optional Latch
  • Low Quiescent Current
  • 5-V to 40-V Operation
  • Thermal Shutdown Protection
  • 16-Pin Dual-In-Line Package

The UC1707-SP power driver is made with a high-speed Schottky process to interface between low-level control functions and high-power switching devices – particularly power MOSFETs. The UC1707-SP contains two independent channels, each of which can be activated by either a high or low input logic level signal. Each output can source or sink up to 1.5 A as long as power dissipation limits are not exceeded.

Although each output can be activated independently with its own inputs, it can be forced low in common through the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The Shutdown command from either source can either be latching or not, depending on the status of the Latch Disable pin.

Supply voltage for both VIN and VC can independently range from 5 to 40 V.

The UC1707-SP power driver is made with a high-speed Schottky process to interface between low-level control functions and high-power switching devices – particularly power MOSFETs. The UC1707-SP contains two independent channels, each of which can be activated by either a high or low input logic level signal. Each output can source or sink up to 1.5 A as long as power dissipation limits are not exceeded.

Although each output can be activated independently with its own inputs, it can be forced low in common through the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The Shutdown command from either source can either be latching or not, depending on the status of the Latch Disable pin.

Supply voltage for both VIN and VC can independently range from 5 to 40 V.

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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 UC1707-SP Dual-Channel Power Driver datasheet (Rev. A) PDF | HTML 2016/3/21
* 輻射及可靠性報告 UC1707-SP (5962-8761903VEA) Neutron Displacement Damage Characterization 2017/11/30
* 輻射及可靠性報告 UC1707-SP SEE Report 2015/3/31
* 輻射及可靠性報告 UC1707-SP ELDRS Report 2015/3/31
* SMD UC1707-SP SMD 5962-87619 2016/7/8
選擇指南 TI Space Products (Rev. L) 2026/3/27
應用說明 Hermetic Package Reflow Profiles, Termination Finishes, and Lead Trim and Form (Rev. A) PDF | HTML 2025/11/5
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025/6/17
應用說明 Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025/6/10
更多文件說明 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025/2/20
應用說明 Why use a Gate Drive Transformer? PDF | HTML 2024/3/4
應用說明 Static Magnet Power Supply Design for Magnetic Resonance Imaging Application PDF | HTML 2024/1/22
應用說明 Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 2024/1/22
應用說明 QML flow, its importance, and obtaining lot information (Rev. C) 2023/8/30
應用說明 Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
應用說明 DLA Standard Microcircuit Drawings (SMD) and JAN Part Numbers Primer 2020/8/21
Application brief External Gate Resistor Selection Guide (Rev. A) 2020/2/28
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020/2/28
電子書 Radiation Handbook for Electronics (Rev. A) 2019/5/21
應用說明 Improving Efficiency of DC-DC Conversion through Layout 2019/5/7
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 2019/1/18
Application brief High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) 2018/11/26

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模擬型號

UC1707 Unencrypted PSpice Transient Model

SLUM648.ZIP (3 KB) - PSpice 模型
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
CFP (W) 16 Ultra Librarian
CDIP (J) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

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