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5.0-V ECL differential buffer

US ECCN: 5A991B1 US/Local Export Classification Number

Inventory: 3,872  

Quality information

RoHS Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-1-260C-UNLIM
Quality, reliability
& packaging information

Information included:

  • RoHS
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (°C)
VSSOP (DGK) | 8 80 | TUBE
-40 to 85
Package | Pins VSSOP (DGK) | 8
Package qty | Carrier: 80 | TUBE
Operating temperature range (°C) -40 to 85
View TI packaging information

Features for the SN65EL16

  • Differential PECL/NECL Receiver
  • Operating Range
    • PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -4.2 V to -5.7 V
  • 250-ps Propagation Delay
  • Support for Clock Frequencies >2 GHz
  • Deterministic Output Value for Open Input Conditions
  • Built-In Temperature Compensation
  • Drop-In Compatible With MC10EL16, MC100EL16
  • Built-In Input Pulldown Resistors
    • Data and Clock Transmission Over Backplane

Description for the SN65EL16

The SN65EL16 is a differential PECL/ECL receiver with PECL/ECL output. The device includes circuitry to hold Q to a low logic level when the inputs are in an open condition.

The VBB pin is a reference voltage output for the device. When the device is used in the single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When the VBB pin is used, place a 0.01-µF decoupling capacitor between VCC and VBB. Also, limit the sink/source current to <0.5 mA to VBB. Leave VBB open when it is not used.

The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.


Qty Price (USD)
1-99 3.006
100-249 2.634
250-999 1.847
1,000+ 1.488