SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

2.9 Over-Scale and Under-Scale

The Over-Scale and Under-Scale Limit circuit provides a programmable upper and lower clip limit for the PGA309 output voltage. This circuit can be enabled by setting Register 5, bit D6 to ‘1’. When combined with the Fault Monitor circuitry, system diagnostics can be performed to determine if a conditioned sensor is defective or if the process being monitored by the sensor is out of range. Figure 2-24 details the key sections of the Over-Scale and Under-Scale Limit circuit. The selected PGA309 VREF is divided down by a precision resistor string to form the over-scale and under-scale thresholds, as shown in Table 2-18 and Table 2-19. Register 5 bits [5:0] set the desired thresholds. These resistor ratios are extremely accurate and produce no significant initial or temperature errors. As shown in Figure 2-24, there are two separate comparators: over-scale and under-scale, which use the over-scale or under-scale threshold, respectively, and determine where the PGA309 output (VOUT) will be clipped. The dominant errors in the Over-Scale and Under-Scale Limit circuit are due to the comparators offset and offset temperature drift.

GUID-8E77DD63-C3E8-4C77-89E9-7493B89DBA92-low.gifFigure 2-24 Over-Scale and Under-Scale Limit Circuit
Table 2-18 Over-Scale Threshold Selections (Register 5 Bits [5:3]). VREF = +5 V
HL2
[5]		 HL1
[4]		 HL0
[3]		 Over-Scale Threshold
(V)		 Over-Scale Threshold
0 0 0 4.854 0.9708 VREF
0 0 1 4.805 0.9610 VREF
0 1 0 4.698 0.9394 VREF
0 1 1 4.580 0.9160 VREF
1 0 0 4.551 0.9102 VREF
1 0 1 3.662 0.7324 VREF
1 1 0 2.764 0.5528 VREF
1 1 1 Reserved —
Table 2-19 Under-Scale Threshold Selections (Register 5 Bits [2:0]). VREF = +5 V
LL2
[2]		 LL1
[1]		 LL0
[0]		 Under-Scale Threshold
(V)		 Under-Scale Threshold
0 0 0 0.127 0.02540 VREF
0 0 1 0.147 0.02930 VREF
0 1 0 0.176 0.03516 VREF
0 1 1 0.196 0.03906 VREF
1 0 0 0.225 0.04492 VREF
1 0 1 0.254 0.05078 VREF
1 1 0 0.274 0.05468 VREF
1 1 1 0.303 0.06054 VREF

The design considerations in using the Over-Scale and Under-Scale Limit circuit are best understood through a definition by example, as shown in Example2-4.