SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

2.1.2 Solving For Gain Settings

An example bridge sensor application will be used to examine internal nodes of the PGA309 that are related to the gain blocks (refer to Figure 2-2 and Figure 2-3).

Given:

Full-Scale Bridge Sensitivity (FSS) = 20mV/V (sensor span)
VOS = 0mV (sensor offset)
VREF = +5V (sensor excitation)
VB = +5V, VS = +5V
RBRG = 2kΩ
VOUT MIN = +0.5V
VOUT MAX= +4.5V

Find:

Front-End PGA Gain
Gain DAC Setting
Zero DAC Setting
Output Amplifier Gain

Solution:

  1. Maximum Sensor Output:
    VBRmax = (FSS)(VB)
    VBRmax = (20mV/V)(5V)
    VBRmax = 100mV
  2. Total Desired Gain:
    GT = (VOUT MAX − VOUT MIN)/VBRmax
    GT = (4.5V − 0.5V)/100mV
    GT = 40
  3. Partition the Gain; Determine the Desired Gain DAC Setting:
    Choose Front-End PGA Gain = 23.27
    Choose Output Amplifier Gain = 2
    Gain DAC = 0.859475719
    Gain DAC = GT/[(Front-End PGA)(Output Amplifier Gain)]
    Gain DAC = 40/[(23.27)(2)]
    Gain DAC = 0.859475719
  4. Calculate exact programmable Gain DAC value:
    Decimal # counts = (Gain DAC − 1/3)(3/2)(65536)
    Decimal # counts = (0.859475719 − 1/3)(3/2)(65536) = 51,721.90133
    Use 51,722 counts→CA0Ah→1100 1010 0000 1010 →0.859476725
    Gain DAC = (# counts/65536)(2/3)+(1/3)
  5. Calculate Zero DAC value
    VZERO DAC = VOUT MIN/[(Gain DAC)(Output Amplifier Gain)]
    VZERO DAC = 0.5V/[(0.859475571)(2)] = 0.29087505V
    Decimal # counts = VZERO DAC/(VREF/65536)
    Decimal # counts = 0.29087505/(5/65536) = 3812.55746
    Use 3813 counts→0EE5h→0000 1110 1110 0101 →0.290908813V
    VZERO DAC = (# counts/65536)(VREF)
  6. Calculate VCM and VDIFF for Maximum Sensor Output (see Figure 2-2): VDIFF = VINP − VINN
    VDIFF = 2.550 − 2.450
    VDIFF = 100mV; VDIFF/2 = 50mV
    VCM = (VINP + VINN)/2
    VCM = (2.550V + 2.450V)/2
    VCM = 2.5V
  7. Check Internal Nodes VOA2 and VOA1: Front-End PGA Gain = 23.27
    G = 5.8175 (see Figure 2-2)
    VOA1 = VCM − G(VDIFF/2)
    VOA1 = 2.5V − 5.8175(50mV)
    VOA1 = 2.209125
    VOA2 = VCM + G(VDIFF/2)
    VOA2 = 2.5V + 5.8175(50mV)
    VOA2 = 2.790875
    0.1V ≤ VOA1 and VOA2 ≤ VS − 0.12V
    0.1V ≤ VOA1 and VOA2 ≤ 4.88V
    Therefore, VOA1 and VOA2 are valid.
  8. Check Internal Nodes VOA3 (VFRONT):
    VFRONT = VDIFF (Front-End PGA Gain) + VZERO DAC
    VDIFF MIN = 0V
    VDIFF MAX = 100mV
    Front-End PGA Gain = 23.27
    VZERO DAC = 0.290908813V
    VFRONT MIN = (0)(23.27) + 0.290908813V = 0.290908813V
    VFRONT MAX = (100mV)(23.27) + 0.290908813V = 2.6179V
    0.05V < VFRONT MIN and VFRONT MAX < VSA − 0.1V
    0.05V < 0.290908813V and 2.6179V < VSA − 0.1V
    VFRONT OK!