SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

GUID-02F0DCAD-B2DD-4452-AEAE-93C536752B33-low.gifFigure 2-14 Corrected Bridge Parabolic Nonlinearity vs Pressure

In each end application, the Linearization Circuit limits should be checked for operation within the allowed range.

Table 2-5 and Table 2-6 illustrate the linearization range for several typical system applications. These tables account for the internal limits of the PGA309 linearization circuit and assume that VOUT scaling is to account for over-scale and under-scale limits and fault detection. For specific end applications not listed, the following equations may be used to calculate critical design values, once the system design choices for VREF, VOUTMAX,VOUTMIN and linearization range, are made:

  1. VEXC MAX: Use Equation 7 at VOUT MAX
  2. VEXC MIN: Use Equation 7 at VOUT MIN
  3. BVMAX (maximum nonlinearity that can be compensated): Use KLIN+MAX to calculate +BVMAX and KLIN–MAX to calculate –BVMAX by Equation 4 solved for BV as:
    GUID-914B3C15-C730-460E-B3AE-41D0620FB934-low.gif
    • For Range 0:
      KLIN −MAX = −0.166
      KLIN +MAX = +0.166
    • For Range 1:
      KLIN −MAX = −0.124
      KLIN +MAX = +0.124
  4. VLin DAC MAX = ((VREF/4) – VOUT MAX/10) ≥ 300mV
  5. VEXC MAX ≤ VSA − 0.5V
  6. KLIN −MAX ≤ KLIN ≤ KLIN +MAX

When using the Linearization Circuit, to ensure that the bridge sensor output common-mode voltage remains within the PGA309 input specifications, Equation 7 can be used to calculate VEXC at full-scale signal (VOUT MAX). The common-mode voltage (VCM) of the bridge sensor output is one-half of VEXC if no common-mode or temperature sensing additional resistor is used in series with the bridge sensor.

During the sensor calibration process using the PGA309, a two-step process can be employed. First, the nonlinearity of the sensor bridge is measured with an initial gain and offset and with KLIN = 0 (Lin DAC set to Zero). Using the resulting sensor nonlinearity (BV), values for KLIN, Gain, and Offset are calculated. A second calibration measurement can be taken to adjust KLIN, to account for any offsets and mismatches in the Linearization Circuit. This calibration procedure is most easily performed using the PGA309 Designer’s Kit and associated software and calibration spreadsheets, which can be downloaded from www.ti.com.

Table 2-4 PGA309 Recommended Operating Conditions
Case1Case2Case3Case4
0.0570.0750.1120.075KLIN +MAX
Range 0
KEXC 0.83 FSS 0.005 V/V
KLIN +MAX –0.166
KLIN –MAX 0.166
Table 2-5 Range 0—Typical System Applications and Maximum Nonlinearity Correction
VSA MIN
(V)		VSA MAX
(V)		VREF
(V)		ADC
REF
(V)		VOUT MIN
(V)		VOUT MAX
(V)		RANGE 0
+BV MAX		RANGE 0
−BV MAX		RANGE 0
+BV
(0.025=
2.5%)		VEXC MAX(1)
(V)		VEXC MIN
(V)		G−BV
(−0.025=
−2.5%)		VEXC MAX
(V)		VEXC MIN
(V)		GLinDAC
MAX
> 0.3V?
(V)
2.75.52.52.50.1752.2250.01362.2022.104167.73−0.04542.0461.706240.380.4025
2.75.52.52.0480.1231.7610.01432.2072.095138.38−0.03542.0551.783183.770.4489
4.55.54.0962.50.1752.1750.02313.7613.429106.36−0.02593.3713.039131.640.8065
4.55.54.0964.0960.2463.5640.03713.9913.441166.26−0.04473.3592.808236.320.6676
4.55.54.0962.0480.1431.7820.01913.6953.42388.70−0.02103.3763.104105.610.8458
4.75.54.54.50.274.1850.02754.2043.780176.76−0.04833.6903.040257.540.7065
55.5550.34.650.01884.4994.200176.76−0.04834.1003.378257.540.785
(1) Limited by VEXC saturation voltage of 0.5V.
Table 2-6 Range 1—Typical System Applications and Maximum Nonlinearity Correction(1)(2)(3)
PGA309
VSA
Operating Range		PGA309
VREF		System
ADC REF		PGA309
VOUT
Linear Range		PGA309
+BV MAX		PGA309
VEXC Range
for +BV MAX		PGA309 Gain
VOUT/
VDIFF IN
for +BV MAX		PGA309
−BV MAX		PGA309
VEXC Range
for −BV MAX		PGA309 Gain
VOUT/
VDIFF IN
for −BV MAX		PGA309
LinDAC
Max Check
VSA MIN
(V)		VSA MAX
(V)		VREF
(V)		ADC
REF
(V)		VOUT MIN
(V)		VOUT MAX
(V)		RANGE 0
+BV MAX		RANGE 0
−BV MAX		RANGE 0
+BV
(0.025=
2.5%)		VEXC MAX
(V)		VEXC MIN
(V)		GT−BV
(−0.025=
−2.5%)		VEXC MAX
(V)		VEXC MIN
(V)		GTLinDAC
MAX
> 0.3V?
(V)
2.75.52.52.50.1752.2250.04391.5761.322260.17−0.05521.2781.024400.350.4025
2.75.52.52.0480.1231.7610.03581.5181.315215.76−0.04291.2851.082302.870.4489
4.55.54.0962.50.1752.1750.02722.4002.152166.69−0.03122.1081.860215.030.8065
4.55.54.0964.0960.2463.5640.04352.5722.160258.02−0.05432.0991.688393.130.6676
4.55.54.0962.0480.1431.7820.02262.3512.148139.44−0.02532.1121.909171.720.8458
4.75.54.54.50.274.1850.04642.8592.373273.88−0.05882.3071.821429.970.7065
55.5550.34.650.04643.1772.637273.88−0.05882.5632.023429.970.785
(1) Over-scale and under-scale limits and fault detection desired.
(2) FSS used to calculate a representative gain value (GT) for completeness.
(3) Range 1, KEXC = 0.52, KLIN −MAX = −0.124, KLIN +MAX = 0.124, FSS = 0.005V/V