SBOU024C august 2004 – july 2023 PGA309
In a power-up or low-voltage event, the POR circuit resets all the PGA309 registers to their initial state. All registers are set to zeros except for the Gain and Zero DACs, which both are set to 4000h.
Table 3-8 summarizes the key settings for the POR states.
Parameter | POR State |
---|---|
Coarse Offset | 0 V |
Front-End PGA Gain | 4 (VIN1 = VINP, VIN2 = VINN) |
Gain DAC | 0.5 |
Output Amplifier Gain | 2 |
Zero DAC | 0.25 VREF |
VREF Select | External Reference |
Lin DAC | 0 |
Fault Monitor | Disabled |
Over/Under-Scale | Disabled |
VEXC | Disabled |
ITEMP | Disabled |
Temp ADC | External Signal Mode |
Example3-2 and Figure 3-5 show by example how the PGA309 functions on power-up with the Test pin high.