SBOU024C august 2004 – july 2023 PGA309
Bit # | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Bit Name | RFB | RFB | RFB | RFB | EXS | EXEN | RS | REN | LD7 | LD6 | LD5 | LD4 | LD3 | LD2 | LD1 | LD0 |
POR Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit Descriptions:
RFB: Reserved Factory Bit: Set to zero for proper operation
EXS: Linearization Adjust and Excitation Voltage (VEXC) Gain Select (Range1 or Range2)
0 = Range 1 (−0.166VFB < Linearization DAC Range < +0.166VFB, VEXC Gain = 0.83VREF)
1 = Range 2 (−0.124VFB < Linearization DAC Range < +0.124VFB, VEXC Gain = 0.52VREF)
EXEN: VEXC Enable
1 = Enable VEXC
0 = Disable VEXC
RS: Internal VREF Select (2.5V or 4.096V)
0 = 4.096V
1 = 2.5V
REN: Enable/Disable Internal VREF (disable for external VREF—connect external VREF to REFIN/REFOUT pin)
0 = External Reference (disable internal reference)
1 = Internal Reference (enable internal reference)
LD[7:0]: Linearization DAC setting, 7-bit + sign
Digital Input (Hex) | Digital Input LD7......LD0 | Linearization Adjust |
---|---|---|
FF | 1111 1111 | −0.166 VFB |
E0 | 1110 0000 | −0.12548 VFB |
C0 | 1100 0000 | −0.08365 VFB |
A0 | 1010 0000 | −0.04183 VFB |
81 | 1000 0001 | −0.00131 VFB |
80 | 1000 0000 | 0 VFB |
00 | 0000 0000 | 0 VFB |
01 | 0000 0001 | +0.00131 VFB |
20 | 0010 0000 | +0.04183 VFB |
40 | 0100 0000 | +0.08365 VFB |
60 | 0110 0000 | +0.12548 VFB |
7F | 0111 1111 | +0.166 VFB |
Linearization DAC Equation:
Decimal # Counts = |Desired VFB Ratio| / (Full-Scale Ratio/127)
Linearization DAC Example:
Given: (Range 1: −0.166VFB < Linearization DAC Range < +0.166VFB)
Want: VFB Ratio = −0.082
Decimal # Counts = 0.082/(0.166/127) = 62.7349
Use 63 counts → 0x3F → 0011 1111
Add a ‘1’ in the Sign Bit (MSB, bit 7) to denote the negative ratio:
Final Linearization DAC Setting: 1011 1111 → BFh