SBOU024C august 2004 – july 2023 PGA309
Fault monitoring of external bridge sensors is provided on the PGA309 through nine internal comparators. Refer to Figure 2-22. These comparators are grouped into two sets: Internal Fault Comparators and External Fault Comparators. In Figure 2-22, these are denoted as EXT for those in the External Fault Comparator group and by INT for those in the Internal Fault Comparator group.
The external fault comparators are used to monitor proper operation of the bridge sensor and report input fault conditions. Table 2-15 enumerates the possible fault cases for a bridge sensor and the associated fault comparator outputs for each fault condition. Due to the extremely low input bias currents of the PGA309, if fault detection of floating inputs (sensor disconnected entirely from one or both of the PGA309 inputs) is to be accurately reported, it is necessary to add either pull-up or pull-down resistors to each of these inputs (VIN1 and VIN2), shown in Figure 2-22 as optional. The value of these resistors can be between 1MΩ and 10MΩ in order to minimize signal loading of the bridge sensor’s output. Offset and other errors from these optional resistors will be cancelled out during the PGA309 + sensor calibration. Table 2-16 itemizes the special cases for floating inputs on the PGA309 when using pull-up resistors. Table 2-17 lists the special cases for floating inputs on the PGA309 when using pull-down resistors. All other fault cases not listed as special cases are the same as those detailed in Table 2-15.
Case | VIN2
(VINN) (V) |
VIN1
(VINP) (V) |
VIA_OUT (V) |
Logic Level Outputs | Comments | |||
---|---|---|---|---|---|---|---|---|
INN_HI (ALM3) |
INN_LO (ALM2) |
INP_HI (ALM1) |
INP_LO (ALM0) |
|||||
Normal | 1.7 | 1.7 | Linear | 0 | 0 | 0 | 0 | |
RB1 Open | 1.7 | 0 | ~0 | 0 | 0 | 0 | 1 | |
RB2 Open | 0 | 1.7 | ~VSA | 0 | 1 | 0 | 0 | |
RB3 Open | 3.4 | 1.7 | ~0 | 1 | 0 | 0 | 0 | |
RB4 Open | 1.7 | 3.4 | ~VSA | 0 | 0 | 1 | 0 | |
RB1 Short | 1.7 | 3.4 | ~VSA | 0 | 0 | 1 | 0 | |
RB2 Short | 3.4 | 1.7 | ~0 | 1 | 0 | 0 | 0 | |
RB3 Short | 0 | 1.7 | ? | 0 | 1 | 0 | 0 | |
RB4 Short | 1.7 | 0 | ~0 | 0 | 0 | 0 | 1 | |
Open Sensor GND | 3.4 | 3.4 | ~0 | 1 | 0 | 1 | 0 | |
Open Sensor VEXC | 0 | 0 | ~0 | 0 | 1 | 0 | 1 | |
VEXC Short GND | 0 | 0 | ~0 | 1(2) | 1 | 1(2) | 1 | |
VIN1 (VINP) Open(3) | 1.7 | ~VSA−0.7 | ~VSA | 0 | 0 | 0 | 0 | Under-scale limit on VOUT, no fault detect—Int or Ext |
VIN2 (VINN) Open(3) | ~VSA−0.7 | 1.7 | ~0 | 0 | 0 | 0 | 0 | Over-scale limit on VOUT, no fault detect—Int or Ext |
VIN1 (VINP) Short GND | 1.7 | 0 | ~0 | 0 | 0 | 0 | 1 | |
VIN2 (VINN) Short GND | 0 | 1.7 | ~VSA | 0 | 1 | 0 | 0 | |
VIN1 (VINP) Short VEXC | 1.7 | 3.4 | ~VSA | 0 | 0 | 1 | 0 | |
VIN2 (VINN) Short VEXC | 3.4 | 1.7 | ~0 | 1 | 0 | 0 | 0 | |
VIN1 (VINP), VIN2 (VINN) Open(3) |
~VSA−0.7 | ~VSA−0.7 | Linear? | 0 | 0 | 0 | 0 | Typically drifts to over-scale limit slowly; no Ext Fault detect (ALM7), Int Fault set = A1 Sat Low |
VIN1 (VINP), VIN2 (VINN) Short GND |
0 | 0 | ~VSA | 0 | 1 | 0 | 1 | |
VIN1 (VINP), VIN2 (VINN) Short VEXC |
3.4 | 3.4 | ~0 | 1 | 0 | 1 | 0 |
Special Case(2) | VIN2
(VINN) (V) |
VIN1
(VINP) (V) |
VIA_OUT (V) |
Logic Level Outputs | |||
---|---|---|---|---|---|---|---|
INN_HI (ALM3) |
INN_LO (ALM2) |
INP_HI (ALM1) |
INP_LO (ALM0) |
||||
VIN1 (VINP) Open | 1.7 | VEXC | ~VSA | 0 | 0 | 1 | 0 |
VIN2 (VINN) Open | VEXC | 1.7 | ~0 | 1 | 0 | 0 | 0 |
VIN1 (VINP), VIN2 (VINN) Open | VEXC | VEXC | ~0 | 1 | 0 | 1 | 0 |
Special Case(2) | VIN2 (VINN) (V) | VIN1 (VINP) (V) | VIA_OUT (V) | Logic Level Outputs | |||
---|---|---|---|---|---|---|---|
INN_HI (ALM3) | INN_LO (ALM2) | INP_HI (ALM1) | INP_LO (ALM0) | ||||
VIN1 (VINP) Open | 1.7 | ~0 | ~VSA | 0 | 0 | 0 | 1 |
VIN2 (VINN) Open | ~0 | 1.7 | ~0 | 0 | 1 | 0 | 0 |
VIN1 (VINP), VIN2 (VINN) Open | ~0 | ~0 | ~0 | 0 | 1 | 0 | 1 |
When VEXC is enabled, external fault comparators INP_HI and INP_LO have a minimum reference selector circuit that selects between a typical trip point of either VEXC – 100mV or VSA – 1.2V. This ensures accurate fault monitoring in conditions where the Linearization Circuit increases VEXC, and the bridge sensor has fault conditions that violate the IVR, relative to VSA, of the Front-End PGA in the PGA309. If VEXC is disabled, these comparators default to the VSA – 1.2V threshold.
The internal fault comparators are used to monitor the Front-End PGA internal nodes of the PGA309 (see Figure 2-22). When PGA309 + Sensor calibration is in process, it is crucial to have the internal comparator group enabled because it can alert the user to an internal node violation. Such a violation may still yield an output voltage within the expected linear range, but it will not be an accurate one. Each of the front-end amplifiers, A1 and A2, of the Front-End PGA have their outputs monitored for both saturation to the positive supply or to ground. If either of these comparators trips during calibration, it is an indication of an out-of-range scaling condition due either to the incorrect Front-End PGA gain select or coarse offset adjust. The A3 amplifier in the Front-End PGA is also monitored for common-mode violations that can occur if the Zero DAC is combined incorrectly with the Front-End PGA gain select.
Each individual internal and external fault comparator can be read through one of the digital interfaces: Two-Wire or One-Wire. The current results are stored in Register 8—Alarm Status Register. When the PGA309 output is enabled, the value of the Alarm Status Register reflects the current state of the fault comparators. When VOUT is disabled, the value in the register is the comparator status immediately before the output was disabled. This allows for easier identification and debugging of a three terminal sensor module (PRG shorted to VOUT). See Section 4.10, One-Wire Operation with PRG Connected to VOUT, for details. In addition, each group of comparators, internal fault and external fault, can be programmed such that if any comparator in their respective group is logic high, indicating a fault, the PGA309 output (VOUT) will be forced to a fault indicating voltage level of either positive (VSA − 0.1V max with a 10kΩ load) or negative (0.1V max with a 10kΩ load). The logic for this is shown in Figure 2-23.
Configuration for the fault monitor comparator logic is provided in Register 5—PGA Configuration and Over/Under Scale Limit. The individual comparator outputs in each group are combined to generate an Internal Comparator Fault flag and an External Comparator Fault flag. For the External Comparator group, EXTEN, Register 5 (bit 11) enables or disables whether the External Comparator Fault flag will be sent forward to force VOUT to a fault indication state. For the Internal Comparator group, INTEN, Register 5 (bit 10), enables or disables whether the Internal Comparator Fault flag will be sent forward to force VOUT to a fault indication state. For each of the comparator groups, there is programmability of the fault indication state on VOUT (either VSA or GND). INTPOL, Register 5 (bit 8), selects this state for the Internal Comparator group and EXTPOL, Register 5 (bit 9) selects for the External Comparator group. The External Comparator Fault flag has priority over the Internal Comparator.
Fault flag, as shown in Figure 2-23. For example, if the Internal Fault Comparator group is set to force VOUT low and the External Fault Comparator group is set to force VOUT high, and both groups detect a fault (which is possible if both are enabled), then the External Fault Comparator group prevails and VOUT is forced high. This is to ensure that for most real-world applications, a critical sensor fault would be reported as priority over an internal node violation. Assuming there is a valid linear output on VOUT at the time of a detected fault, the fault logic always prevails (if enabled), and will override the linear output to indicate a fault on VOUT as positive or negative VOUT saturation.