SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

GUID-BD523494-B737-4865-B2B9-5C50D84B1BA2-low.gif
(Although not needed in all applications):
  1. RISO and RFB provide the PGA309 with overvoltage protection on Sensor Out.
  2. CL provides EMI/RFI filtering.
  3. CF provides the PGA309 with stability for capacitive load of CL.
Figure 2-25 Absolute Scale System—PGA309 Connected to a System ADC
Table 2-20 Electrical Characteristics for Over-Scale and Under-Scale Comparators and VREF
Parameter Min Typ Max Units
Over-Scale Comparator Offset +6 +60 +114 mV
Over-Scale Comparator Offset Drift +0.37 mV/°C
Under-Scale Comparator Offset −7 −50 −93 mV
Under-Scale Comparator Offset Drift −0.15 mV/°C
VREF2 4.00 4.096 4.14 V
VREF2 Drift +10 ppm/°C
Table 2-21 Over-Scale and Under-Scale Min and Max Trip Point Calculations(1)
Threshold
U = Under-Scale
O = Over-Scale		 Threshold
Ratio to VREF		 Min Trip
(V)		 Min Trip
(%VREF ADC)		 Max Trip
(V)		 Max Trip
(%VREF ADC)		 Typ Trip
(V)		 Typ Trip
(%VREF ADC)
U7 0.0605 0.1338 3.2656 0.2483 6.0616 0.1910 4.6636
U6 0.0547 0.1104 2.6943 0.2240 5.4684 0.1672 4.0814
U5 0.0508 0.0948 2.3141 0.2078 5.0736 0.1513 3.6938
U4 0.0449 0.0714 1.7428 0.1835 4.4804 0.1274 3.1116
U3 0.0391 0.0480 1.1714 0.1592 3.8871 0.1036 2.5293
U2 0.0352 0.0324 0.7912 0.1430 3.4923 0.0877 2.1418
U1 0.0293 0.0090 0.2199 0.1187 2.8991 0.0639 1.5595
U0 0.0254 −0.0066 −0.1603 0.1026 2.5042 0.0480 1.1719
O6 0.5528 2.1895 53.4546 2.4432 59.6494 2.3164 56.5520
O5 0.7324 2.9067 70.9648 3.1880 77.8313 3.0473 74.3980
O4 0.9102 3.6167 88.2994 3.9252 95.8309 3.7710 92.0652
O3 0.9160 3.6399 88.8649 3.9493 96.4181 3.7946 92.6415
O2 0.9394 3.7333 91.1462 4.0463 98.7870 3.8898 94.9666
O1 0.9610 3.8196 93.2521 4.1359 100.9737 3.9777 97.1129
O0 0.9708 3.8587 94.2076 4.1765 101.9658 4.0176 98.0867
(1) VREF MIN = 3.9934V, VREF MAX = 4.1466V, VREF ADC = 4.096V, VOS min = −0.01805V, VOS max = 0.151V,
VUS min = −0.00275V, VUS max = −0.108V. Bold Italics indicate final choice for Example2-4.
GUID-29C9DF52-D097-4004-A194-03239434BA5F-low.gifFigure 2-26 System ADC Range Budget for Over-Scale, Under-Scale, and Linear Output
Table 2-22 PGA309 VOUT Limits for System ADC Range Budget(1)
Limiting Condition PGA309 VOUT (V) PGA309 VOUT Limit (V)
96.4% VREF ADC—Over-Scale Limit (max) 3.9493 4.9
3.3% VREF ADC—Under-Scale Limit (min) 0.1338 0.1
(1) VREF ADC = 4.096V, VSA = 5V.