Now, clear the trip by writing 1 to the CLLLC_clearTrip variable.
In the watch view, check if the CLLLC_vPrimSensed_Volts,
CLLLC_iPrimSensed_Amps, CLLLC_vSecSensed_Volts, and CLLLC_iSecSensed_Amps
variables are updating periodically. (Note: As no power is applied right now,
these will be close to zero.)
Now, slowly increase the input VPRIM DC voltage from 0 V to
400 V. Make sure CLLLC_vPrimSensed_Volts displays the correct values.
By default, the CLLLC_pwmPeriodRef_pu variable is set to 0.599, as shown in
Figure 5-10,
which is 500.8 kHz. This is close to the series resonant frequency of the
converter; however, due to variation in the components on the actual hardware,
it can be lower or higher than the series resonant frequency. For example, in
Figure 5-11, we see frequency slightly lower than series resonant frequency.
The VSEC variable will show a voltage of close to 300 V per
the tank gain designed. Verify that CLLLC_vSecSensed_Volts shows the correct
voltage. This verifies the voltage sensing on the board.
Figure 5-10 Lab 2 Expression Window, at
Resonance
With the load specified in the test conditions, the current
from the PRIM and SEC side will be close to 4.8 A for CLLLC_iPrimSensed_Amps,
and 6.8 A for CLLLC_iSecSensed_Amps.
Figure 5-11 Lab 2, Primary (ch2) and
Secondary (ch3) Currents at Resonance
Next, to see operation under different frequencies
(that is, above resonance, below resonance), change the CLLLC_pwmPeriodRef_pu
variable to be 0.47 which will correspond to a frequency of 639 kHz. The
waveform under this condition is shown in Figure 5-12.
Figure 5-12 Lab 2, Primary (ch2) and
Secondary (ch3) Currents Above Series Resonance Frequency
Next, test behavior with lower than series resonant frequency by entering 0.8
as the CLLLC_pwmPeriodRef_pu, which will make generate frequency of 374 kHz. In
this case, the primary current will become discontinuous and the secondary side
duty cycle will modulate to achieve diode emulation shown in Figure 5-13.
This verifies at a basic level the PWM driver and connection
of hardware.
Figure 5-13 Lab 2, Primary (ch2) and
Secondary (ch3) Currents Below Series Resonance Frequency