TIDUF18A October   2022  – February 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 CLLLC System Description
    1. 1.1 Key System Specifications
  8. 2 CLLLC System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations and System Design Theory
      1. 2.2.1 Tank Design
        1. 2.2.1.1 Voltage Gain
        2. 2.2.1.2 Transformer Gain Ratio Design (NCLLLC)
        3. 2.2.1.3 Magnetizing Inductance Selection (Lm)
        4. 2.2.1.4 Resonant Inductor and Capacitor Selection (Lrp and Crp)
      2. 2.2.2 Current and Voltage Sensing
        1. 2.2.2.1 VPRIM Voltage Sensing
        2. 2.2.2.2 VSEC Voltage Sensing
        3. 2.2.2.3 ISEC Current Sensing
        4. 2.2.2.4 ISEC TANK and IPRIM TANK
        5. 2.2.2.5 IPRIM Current Sensing
        6. 2.2.2.6 Protection (CMPSS and X-Bar)
      3. 2.2.3 PWM Modulation
  9. 3 Totem Pole PFC System Description
    1. 3.1 Benefits of Totem-Pole Bridgeless PFC
    2. 3.2 Totem-Pole Bridgeless PFC Operation
    3. 3.3 Key System Specifications
    4. 3.4 System Overview
      1. 3.4.1 Block Diagram
    5. 3.5 System Design Theory
      1. 3.5.1 PWM
      2. 3.5.2 Current Loop Model
      3. 3.5.3 DC Bus Regulation Loop
      4. 3.5.4 Soft Start Around Zero-Crossing for Eliminating or Reducing Current Spike
      5. 3.5.5 Current Calculation
      6. 3.5.6 Inductor Calculation
      7. 3.5.7 Output Capacitor Calculation
      8. 3.5.8 Current and Voltage Sense
  10. 4 Highlighted Products
    1. 4.1 C2000 MCU TMS320F28003x
    2. 4.2 LMG352xR30-Q1
    3. 4.3 UCC21222-Q1
    4. 4.4 AMC3330-Q1
    5. 4.5 AMC3302-Q1
  11. 5 Hardware, Software, Testing Requirements, and Test Results
    1. 5.1 Required Hardware and Software
      1. 5.1.1 Hardware Settings
        1. 5.1.1.1 Control Card Settings
      2. 5.1.2 Software
        1. 5.1.2.1 Opening the Project Inside Code Composer Studio
        2. 5.1.2.2 Project Structure
    2. 5.2 Testing and Results
      1. 5.2.1 Test Setup (Initial)
      2. 5.2.2 CLLLC Test Procedure
        1. 5.2.2.1 Lab 1. Primary to Secondary Power Flow, Open Loop Check PWM Driver
        2. 5.2.2.2 Lab 2. Primary to Secondary Power Flow, Open Loop CheckPWM Driver and ADC with Protection, Resistive Load Connected on Secondary
          1. 5.2.2.2.1 Setting Software Options for Lab 2
          2. 5.2.2.2.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.2.3 Using Real-time Emulation
          4. 5.2.2.2.4 Running the Code
          5. 5.2.2.2.5 Measure SFRA Plant for Voltage Loop
          6. 5.2.2.2.6 Verify Active Synchronous Rectification
          7. 5.2.2.2.7 Measure SFRA Plant for Current Loop
        3. 5.2.2.3 Lab 3. Primary to Secondary Power Flow, Closed Voltage Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.3.1 Setting Software Options for Lab 3
          2. 5.2.2.3.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.3.3 Running the Code
          4. 5.2.2.3.4 Measure SFRA for Closed Voltage Loop
        4. 5.2.2.4 Lab 4. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.4.1 Setting Software Options for Lab 4
          2. 5.2.2.4.2 Building and Loading the Project and Setting up Debug
          3. 5.2.2.4.3 Running the Code
          4. 5.2.2.4.4 Measure SFRA for Closed Current Loop
        5. 5.2.2.5 Lab 5. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary in Parallel to a Voltage Source to Emulate a Battery Connection on Secondary Side
          1. 5.2.2.5.1 Setting Software Options for Lab 5
          2. 5.2.2.5.2 Designing Current Loop Compensator
          3. 5.2.2.5.3 Building and Loading the Project and Setting up Debug
          4. 5.2.2.5.4 Running the Code
          5. 5.2.2.5.5 Measure SFRA for Closed Current Loop in Battery Emulated Mode
      3. 5.2.3 TTPLPFC Test procedure
        1. 5.2.3.1 Lab 1: Open Loop, DC
          1. 5.2.3.1.1 Setting Software Options for BUILD 1
          2. 5.2.3.1.2 Building and Loading Project
          3. 5.2.3.1.3 Setup Debug Environment Windows
          4. 5.2.3.1.4 Using Real-Time Emulation
          5. 5.2.3.1.5 Running Code
        2. 5.2.3.2 Lab 2: Closed Current Loop DC
          1. 5.2.3.2.1 Setting Software Options for BUILD 2
          2. 5.2.3.2.2 Designing Current Loop Compensator
          3. 5.2.3.2.3 Building and Loading Project and Setting Up Debug
          4. 5.2.3.2.4 Running Code
        3. 5.2.3.3 Lab 3: Closed Current Loop, AC
          1. 5.2.3.3.1 Setting Software Options for Lab 3
          2. 5.2.3.3.2 Building and Loading Project and Setting Up Debug
          3. 5.2.3.3.3 Running Code
        4. 5.2.3.4 Lab 4: Closed Voltage and Current Loop
          1. 5.2.3.4.1 Setting Software Options for BUILD 4
          2. 5.2.3.4.2 Building and Loading Project and Setting up Debug
          3. 5.2.3.4.3 Running Code
      4. 5.2.4 Test Results
        1. 5.2.4.1 Efficiency
        2. 5.2.4.2 System Performance
        3. 5.2.4.3 Bode Plots
        4. 5.2.4.4 Efficiency and Regulation Data
        5. 5.2.4.5 Thermal Data
        6. 5.2.4.6 PFC Waveforms
        7. 5.2.4.7 CLLLC Waveforms
  12. 6 Design Files
    1. 6.1 Schematics
    2. 6.2 Bill of Materials
    3. 6.3 Altium Project
    4. 6.4 Gerber Files
  13. 7 Software Files
  14. 8 Related Documentation
    1. 8.1 Trademarks
  15. 9 Terminology
  16. 10About the Author
  17. 11Revision History

5.1.1 Hardware Settings

The design follows a High-Speed Edge Card (HSEC) control card concept, and any device for which a HSEC control card is available from the C2000 MCU product family can be potentially used on this design. The key resources used for controlling the power stage on the microcontroller are listed in Table 5-1. Figure 5-1 shows the key power stage and connectors on the reference design. Table 5-3 lists the key connectors and their functions.

  1. Make sure no power source is connected to the board.
  2. Insert the control card in the J25 slot.
  3. Connect a power source (but do not power up) for the 12V bias supplies (+12 V, 2 A) at the J15 shown in Figure 5-1.
  4. Now, switch the power source on for the bias supply. A green LED on the control card will light up. This indicates the C2000 MCU device is powered. Note: The bias for the microcontroller is separated from the power stage; this enables a safe bring up of the system in this set of instructions.
  5. To connect JTAG, use a USB cable from the control card and connect it to a host computer.
  6. For operation of the TTPLPFC stage an AC input must be connected to J33 (90V - 264V). For testing a >10kW supply has been used, however a clean and stable lower-rated supply can be used in the case where only low-power tests are being conducted.
  7. For stand alone operation of the PFC stage a load may be connected to J37 and J38, alternatively the CLLLC can be used to load the PFC stage.
  8. For stand alone operation of the CLLLC stage a DC power supply (400V) may be connected to VBUS at J15. If this is done the TTPLPFC should not be started in software and the AC source described in step 6 above should not be connected.
  9. A load should be connected to the secondary side of the CLLLC converter when in use. J7 and J10 can be used to connect such a load.
  10. When operating both the PFC and DCDC stages connect an AC supply as in Step 6 above and a load as in step 9 above. No connection to VBUS is needed however a current bleed resistor may be helpful to ensure excess voltage can be quickly bled off after execution of the OBC.
  11. Current and voltage probes can be connected to observe the tank current at primary and secondary. Optionally, a power meter can be connected to measure the efficiency.
GUID-20220928-SS0I-XVQ1-DG5R-SX6K6JDLCJRM-low.pngFigure 5-1 Board Overview

There are 7 bias supply daughter cards required shown in red

GUID-20220928-SS0I-ZTT2-RJX1-FKBCK1TH93DD-low.png Figure 5-2 PMP22712 - bias supplies

There is one Feedback isolation daughter card PMP22773 required indicated in red

GUID-20220928-SS0I-QPXT-KVSG-GNMFTDDM7BQB-low.png Figure 5-3 PMP22773 – Feedback Isolation Daughter Card
Table 5-1 Key Digital Pin Assignments
Signal name HSEC Pin Number F28003x peripheral
SYSTEM ISR Trigger - ECAP1
CLLLC_CONTROL_OUTPUT_DAC_PIN 14 DACA
CLLLC_PRIM_LEG1_H/L 49/ 51 EPWM1 (A/B)
CLLLC_PRIM_LEG2_H/L 53/ 55 EPWM2 (A/B)
CLLLC_SEC_LEG1_H/L 50/ 52 EPWM3 (A/B)
CLLLC_SEC_LEG2_H/L 54/ 56 EPWM4 (A/B)
CLLLC_FAULTn 74 GPIO-23 → INPUTXBAR2
CLLLC_LC_CHANGE 62 GPIO-14
CLLLC_SEC_SIDE_DIAG 80 GPIO-30
TTPLPFC_LOW_FREQ_H/L 57/ 59 EPWM5 (A/B)
TTPLPFC_HIGH_FREQ_PH1_H/L 61/ 63 EPWM6 (A/B)
TTPLPFC_HIGH_FREQ_PH2_H/L 58/ 60 EPWM7 (A/B)
TTPLPFC_FAULTn 72 GPIO-22 → INPUTXBAR1
TTPLPFC_INRUSH_RELAY_CTRL 64 GPIO-15
ERRORSTSn 102 GPIO55

SYSTEM_WATCHDOG_OUT

SYSTEM_WATCHDOG_DISABLE

SYSTEM_PMIC_SPI (resv)

SYSTEM_PMIC_SPI (resv)

75

77

79

81

GPIO24

GPIO25(Resistor option)

GPIO26(Resistor option)

GPIO27(Resistor option)
SYSTEM_DISABLE_FET_SUPPLY 85 GPIO32

SYSTEM_TEMP_MUX_OUT1

SYSTEM_TEMP_MUX_OUT2

91

96

GPIO41 -> ECAP2 → INPUTXBAR3

GPIO60 -> ECAP3 → INPUTXBAR4
SYSTEM_TEMP_MUX_SEL_1-3

93

94

95

GPIO47

GPIO58

GPIO59

SYSTEM_PROFILING1-3

89

92

101

GPIO40

GPIO44

GPIO49

FSI_TX_D0

FSI_TX_D1

FSI_TX_CLK

101

103

105

GPIO-49/FSITXA_D0

GPIO-50/FSITXA_D1

GPIO-51/FSITXA_CLK

LED1

LED2

82

86

GPIO-31 → LED1

GPIO-34 → LED2 (SFRA)

This table describes the sampling scheme for the reference design. Across the top each column represents one independent ADC. Each ADC acts entirely independently from the others. Each signal is assigned one or more Start Of Conversions (SOCs). Each SOC represents one independent reading of that channel, for example TTPLPFC_IAC_PH1 is assigned SOC0 and SOC1 within ADCA. This means that this signal will be sampled twice every cycle, once triggered by ePWM6_SOCA and once triggered by ePWM6_SOCB. Since this trigger is running at 120kHz this signal is effectively oversampled by a factor of two times during each 120kHz sampling period. Similarly CLLLC_ISEC is oversampled 11 times, and CLLLC_IPRIM is not oversampled. The table also indicates several low-frequency sampled signals which can be seen that these signals use a different SOC signal. Finally since a round robin counter is used to process the SOCs in numeric order the table reads as a timeline from top to bottom in the order of sampling.

Table 5-2 Key Analog Signals
ADC-A ADC-B ADC-C

Highest Priority Signals

(120kHz)

TTPLPFC_IAC_PH1 (A2, CMPSS1)

SOC0 → ADC_TRIGGER_EPWM6_SOCA

SOC1 → ADC_TRIGGER_EPWM6_SOCB

TTPLPFC_IAC_PH2 (B12, CMPSS3)

SOC0 → ADC_TRIGGER_EPWM6_SOCA

SOC1 → ADC_TRIGGER_EPWM6_SOCB

TTPLPFC_VAC (C7)

SOC0 → ADC_TRIGGER_EPWM6_SOCA

SOC1 → ADC_TRIGGER_EPWM6_SOCB

CLLLC_ISEC (A5, CMPSS2)

SOC2 → ADC_TRIGGER_EPWM6_SOCA

SOC3 → ADC_TRIGGER_EPWM6_SOCA

SOC4 → ADC_TRIGGER_EPWM6_SOCA

SOC5 → ADC_TRIGGER_EPWM6_SOCA

SOC6 → ADC_TRIGGER_EPWM6_SOCA

SOC7 →ADC_TRIGGER_EPWM6_SOCA

SOC8 → ADC_TRIGGER_EPWM6_SOCB

SOC9 → ADC_TRIGGER_EPWM6_SOCB

SOC10 → ADC_TRIGGER_EPWM6_SOCB

SOC11 → ADC_TRIGGER_EPWM6_SOCB

SOC12 → ADC_TRIGGER_EPWM6_SOCB

TTPLPFC_VBUS / CLLLC_VBUS (B4)

SOC2 → ADC_TRIGGER_EPWM6_SOCA

SOC3 → ADC_TRIGGER_EPWM6_SOCB

SOC4 → ADC_TRIGGER_EPWM7_SOCA

SOC5 → ADC_TRIGGER_EPWM7_SOCB

CLLLC_VSEC (C11, CMPSS2)

SOC2 → ADC_TRIGGER_EPWM6_SOCA

SOC3 → ADC_TRIGGER_EPWM6_SOCA

SOC4 → ADC_TRIGGER_EPWM6_SOCA

SOC5 → ADC_TRIGGER_EPWM6_SOCA

SOC6 → ADC_TRIGGER_EPWM6_SOCA

SOC7 → ADC_TRIGGER_EPWM6_SOCA

SOC8 → ADC_TRIGGER_EPWM6_SOCA

SOC9 → ADC_TRIGGER_EPWM6_SOCA

SOC10 → ADC_TRIGGER_EPWM6_SOCA

SOC11 → ADC_TRIGGER_EPWM6_SOCA

SOC12 → ADC_TRIGGER_EPWM6_SOCA

CLLLC_IPRIM (A9, CMPSS2)

SOC13→ADC_TRIGGER_EPWM1_SOCA

Low-Frequency Sampling Signals

(10kHz)

TTPLPFC_VAC_L (A4)

SOC14 →ADC_TRIGGER_CPU1_TINT2

TTPLPFC_VAC_N (B2)

SOC10 → ADC_TRIGGER_CPU1_TINT2

TTPLPFC_VBUS2 (C10, CMPSS2)

SOC14 → ADC_TRIGGER_CPU1_TINT2

SYSTEM_ TEMP_1 (A11)

SOC15 → ADC_TRIGGER_CPU1_TINT2

SYSTEM_VREF_1_65 (B5)

SOC11 →ADC_TRIGGER_CPU1_TINT2

CLLLC_VSEC (C11, CMPSS2)

VSEC13 → SOC15 →ADC_TRIGGER_CPU1_TINT2
Not Sampled, CMPSS only CLLLC_IPRIM_TANK (A12/C5, CMPSS2) CLLLC_ISEC_TANK (C1, CMPSS4)
Table 5-3 Key Connectors and Their Function
CONNECTOR NAME FUNCTION
J33 AC input
J37/J38 VBUS connection; PFC output, DCDC VPRIM
J7/J10 DCDC output connection; DCDC VSEC
J15 12 V 2 A power supply
J25/J26 HSEC control card connector slot