TIDUF18A October   2022  – February 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 CLLLC System Description
    1. 1.1 Key System Specifications
  8. 2 CLLLC System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations and System Design Theory
      1. 2.2.1 Tank Design
        1. 2.2.1.1 Voltage Gain
        2. 2.2.1.2 Transformer Gain Ratio Design (NCLLLC)
        3. 2.2.1.3 Magnetizing Inductance Selection (Lm)
        4. 2.2.1.4 Resonant Inductor and Capacitor Selection (Lrp and Crp)
      2. 2.2.2 Current and Voltage Sensing
        1. 2.2.2.1 VPRIM Voltage Sensing
        2. 2.2.2.2 VSEC Voltage Sensing
        3. 2.2.2.3 ISEC Current Sensing
        4. 2.2.2.4 ISEC TANK and IPRIM TANK
        5. 2.2.2.5 IPRIM Current Sensing
        6. 2.2.2.6 Protection (CMPSS and X-Bar)
      3. 2.2.3 PWM Modulation
  9. 3 Totem Pole PFC System Description
    1. 3.1 Benefits of Totem-Pole Bridgeless PFC
    2. 3.2 Totem-Pole Bridgeless PFC Operation
    3. 3.3 Key System Specifications
    4. 3.4 System Overview
      1. 3.4.1 Block Diagram
    5. 3.5 System Design Theory
      1. 3.5.1 PWM
      2. 3.5.2 Current Loop Model
      3. 3.5.3 DC Bus Regulation Loop
      4. 3.5.4 Soft Start Around Zero-Crossing for Eliminating or Reducing Current Spike
      5. 3.5.5 Current Calculation
      6. 3.5.6 Inductor Calculation
      7. 3.5.7 Output Capacitor Calculation
      8. 3.5.8 Current and Voltage Sense
  10. 4 Highlighted Products
    1. 4.1 C2000 MCU TMS320F28003x
    2. 4.2 LMG352xR30-Q1
    3. 4.3 UCC21222-Q1
    4. 4.4 AMC3330-Q1
    5. 4.5 AMC3302-Q1
  11. 5 Hardware, Software, Testing Requirements, and Test Results
    1. 5.1 Required Hardware and Software
      1. 5.1.1 Hardware Settings
        1. 5.1.1.1 Control Card Settings
      2. 5.1.2 Software
        1. 5.1.2.1 Opening the Project Inside Code Composer Studio
        2. 5.1.2.2 Project Structure
    2. 5.2 Testing and Results
      1. 5.2.1 Test Setup (Initial)
      2. 5.2.2 CLLLC Test Procedure
        1. 5.2.2.1 Lab 1. Primary to Secondary Power Flow, Open Loop Check PWM Driver
        2. 5.2.2.2 Lab 2. Primary to Secondary Power Flow, Open Loop CheckPWM Driver and ADC with Protection, Resistive Load Connected on Secondary
          1. 5.2.2.2.1 Setting Software Options for Lab 2
          2. 5.2.2.2.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.2.3 Using Real-time Emulation
          4. 5.2.2.2.4 Running the Code
          5. 5.2.2.2.5 Measure SFRA Plant for Voltage Loop
          6. 5.2.2.2.6 Verify Active Synchronous Rectification
          7. 5.2.2.2.7 Measure SFRA Plant for Current Loop
        3. 5.2.2.3 Lab 3. Primary to Secondary Power Flow, Closed Voltage Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.3.1 Setting Software Options for Lab 3
          2. 5.2.2.3.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.3.3 Running the Code
          4. 5.2.2.3.4 Measure SFRA for Closed Voltage Loop
        4. 5.2.2.4 Lab 4. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.4.1 Setting Software Options for Lab 4
          2. 5.2.2.4.2 Building and Loading the Project and Setting up Debug
          3. 5.2.2.4.3 Running the Code
          4. 5.2.2.4.4 Measure SFRA for Closed Current Loop
        5. 5.2.2.5 Lab 5. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary in Parallel to a Voltage Source to Emulate a Battery Connection on Secondary Side
          1. 5.2.2.5.1 Setting Software Options for Lab 5
          2. 5.2.2.5.2 Designing Current Loop Compensator
          3. 5.2.2.5.3 Building and Loading the Project and Setting up Debug
          4. 5.2.2.5.4 Running the Code
          5. 5.2.2.5.5 Measure SFRA for Closed Current Loop in Battery Emulated Mode
      3. 5.2.3 TTPLPFC Test procedure
        1. 5.2.3.1 Lab 1: Open Loop, DC
          1. 5.2.3.1.1 Setting Software Options for BUILD 1
          2. 5.2.3.1.2 Building and Loading Project
          3. 5.2.3.1.3 Setup Debug Environment Windows
          4. 5.2.3.1.4 Using Real-Time Emulation
          5. 5.2.3.1.5 Running Code
        2. 5.2.3.2 Lab 2: Closed Current Loop DC
          1. 5.2.3.2.1 Setting Software Options for BUILD 2
          2. 5.2.3.2.2 Designing Current Loop Compensator
          3. 5.2.3.2.3 Building and Loading Project and Setting Up Debug
          4. 5.2.3.2.4 Running Code
        3. 5.2.3.3 Lab 3: Closed Current Loop, AC
          1. 5.2.3.3.1 Setting Software Options for Lab 3
          2. 5.2.3.3.2 Building and Loading Project and Setting Up Debug
          3. 5.2.3.3.3 Running Code
        4. 5.2.3.4 Lab 4: Closed Voltage and Current Loop
          1. 5.2.3.4.1 Setting Software Options for BUILD 4
          2. 5.2.3.4.2 Building and Loading Project and Setting up Debug
          3. 5.2.3.4.3 Running Code
      4. 5.2.4 Test Results
        1. 5.2.4.1 Efficiency
        2. 5.2.4.2 System Performance
        3. 5.2.4.3 Bode Plots
        4. 5.2.4.4 Efficiency and Regulation Data
        5. 5.2.4.5 Thermal Data
        6. 5.2.4.6 PFC Waveforms
        7. 5.2.4.7 CLLLC Waveforms
  12. 6 Design Files
    1. 6.1 Schematics
    2. 6.2 Bill of Materials
    3. 6.3 Altium Project
    4. 6.4 Gerber Files
  13. 7 Software Files
  14. 8 Related Documentation
    1. 8.1 Trademarks
  15. 9 Terminology
  16. 10About the Author
  17. 11Revision History

5.1.2.2 Project Structure

GUID-78DC4A25-199A-44F9-BA8F-85C1733347AF-low.gifFigure 5-4 Project Structure Overview

The general structure of the project is shown in Figure 5-4. Once the project is imported, the Project Explorer will appear inside CCS as shown in Figure 5-5.

Solution-specific and device-independent files that consist of the core algorithmic code are in <solution>.c/h. For example TTPLPFC.c or CLLLC.h.

Board-specific and device-specific files are in <solution>_hal.c/h. This file consists of device-specific drivers to run the solution. If the user wants to use a different modulation scheme or a different device, the user is required only to make changes to these files, besides changing the device support files in the project.

The <solution>-main.c file consists of the main framework of the project. This file consists of calls to the board and solution file that help in creating the system framework, along with the interrupt service routines (ISRs) and slow background tasks.

For this design, there are three <solution> monikers obc_7_4kw, clllc, and ttplpfc. Please note that to maintain maximum flexibility we have chosen to keep the CLLLC code base and the TTPLPFC code base as independent as possible while the obc_7_4kw files were added where needed to contain settings independent to the TTPLPFC and CLLLC. This allows the end user to operate each stage independently and incorporate different topologies for either the PFC or DCDC stages easily in their final design if desired.

The <solution>_settings.h file contains code configuration settings like which lab to build. While the <solution>_user_settings.h contains the board level configurations such as #defines for ADC mapping, GPIOs etc.

solution.js files contain a script file which can help populate relevant variables to observer during the execution of each lab. To use these scripts open the scripting console(View - Scripting Console). Paste the contents of the solution.js file into the scripting console and press enter. This will populate the expressions window for debug later.

The solution name is also used as the module name for all the variables and defines used in the solution. Hence, all variables and function calls are prepended by the CLLLC name (for example, CLLLC_vSecSensed_pu). This naming convention lets the user combine different solutions while avoiding naming conflicts.

GUID-20220928-SS0I-NWQP-3BGF-1PRM0B9S5KRG-low.pngFigure 5-5 Project Explorer View of the CLLLC Project

The OBC project consists of three ISRs (ISR1, ISR2, and ISR3) running on 2 cores, the C28x core and the CLA core. Using an ePWM for the ISR1 trigger, an eCAP for ISR2's trigger, and ADC for ISR3's trigger allows the ISR priority to be controlled entirely by hardware. Table 5-4 shows how each ISR is partitioned and its tasks.

Table 5-4 ISR Partitions and Tasks
ISRTrigger sourceC28xCLA
ISR1 (120kHz)ePWMN/AUpdate CLLLC PWM values
ISR2 (120kHz)eCAPPFC current loopCLLLC control code, enable ISR1
ISR3 (10kHz)ADCPFC voltage loop, instrumentationN/A

ISR1 is the fastest and non-nestable ISR reserved for PWM updates and is ran entirely on CLA. ISR1 is triggered by the PRIM_LEG1_PWM_BASE → EPWM_INT_TBCTR_U_CMPC event. In general, this interrupt is disabled by writing a value to CMPC, which is greater than all possible TBPRD register values for PRIM_LEG1_PWM_BASE. This is done through the CLLLC_HAL_setupISR1Trigger function. Following are the defines that are related to this ISR.

#define CLLLC_ISR1_PERIPHERAL_TRIG_BASE CLLLC_PRIM_LEG1_PWM_BASE
#define CLLLC_ISR1_TRIG INT_EPWM1
#define CLLLC_ISR1_PIE_GROUP INTERRUPT_ACK_GROUP3

#define CLLLC_ISR1_TRIG_CLA CLA_TRIGGER_EPWM1INT

ISR2 is split across both cores. This allows a simple modular code segregation for the TTPLPFC and CLLLC code. Both the ISR2 ran on the C28x and the ISR2 ran on the CLA are triggered by the same source and operate in tandem. The C28x core run task related to the TTPLPFC while the CLA core runs task related to the CLLLC's execution.

ISR2 is responsible for writing a valid value to trigger ISR1 by a write to CMPC when ISR1 is desired. (Note: The CMPC is not tied to the global load mechanism to enable this. Also, shadow load of CMPC is disabled.) The CMPC value can be adjusted to get the desired timing from the ISR1. Each time ISR1 is enabled, it triggers two times. In the first ISR1, PWM registers are updated and a sync is enabled. In the second ISR1, the PWM sync is disabled and CMPC is set to a value such that ISR1 does not trigger again. For simplicity the software diagrams and structure only show ISR1 that is triggered the first time.

ISR2 is periodically triggered at ISR2_FREQUENCY. A spare CAP module is used to generate the time base and trigger the interrupt. A spare ePWM module is also configured with the same time base and is used to trigger the ADC conversions. ISR2 is responsible for running the control law and calculating the clock ticks required for the PWM. Once the writes to the shadow registers are complete, the ISR2 enables the ISR1 trigger by writing a valid value (that is, one that is less than the current TBPRD register) to the CMPC register. ISR2 has two variants ISR2_primToSecPowerFlow and ISR2_secToPrimPowerFlow, one for the power flow from primary to secondary side and other for secondary to primary. This is done to optimize CPU cycles when controlling power flow in different directions. For simplicity of explanation either of them are just referred to as ISR2 in respective labs. Depending on the timing, the ISR1 may nest ISR2 for the update writes, which are very timing-critical. Following are the defines that are related to this ISR.

#define CLLLC_ISR2_ECAP_BASE ECAP1_BASE
#define CLLLC_ISR2_PWM_BASE EPWM5_BASE
#define CLLLC_ISR2_TRIG INT_ECAP1
#define CLLLC_ISR2_PIE_GROUP INTERRUPT_ACK_GROUP4
#define CLLLC_ISR2_TRIG_CLA CLA_TRIGGER_ADCA2

ISR3 is ran entirely on the C28x core and is triggered by ADCINT2. ADCINT2 is initiated by a conversion that is started using a CPU timer. It is used to run the TTPLPFC's voltage loop as well as housekeeping functions such as doing a running average on the currents and voltage signals to remove noise. Even so much as running the slew rate function for commanded references.

#define CLLLC_ISR3_TIMEBASE CLLLC_TASKC_CPUTIMER_BASE
#define CLLLC_ISR3_PERIPHERAL_TRIG_BASE ADCC_BASE
#define CLLLC_ISR3_TRIG INT_ADCC2
#define CLLLC_ISR3_PIE_GROUP INTERRUPT_ACK_GROUP10

With this, the interrupts can be nested easily. Figure 5-6 shows the nesting of the three interrupts occurring. The image is taken for the system in open loop and when a period change is initiated through the watch window, hence only one time ISR1 trigger is observed. For a closed-loop system, the period will only have minor changes from one control ISR cycle to the other and hence the ISR1 will be triggered repeatedly.

GUID-31F7A8E1-37F7-4527-B202-0CA6CED227A7-low.gifFigure 5-6 Three-Level Nested ISRs

Additionally, CPU timers are used to trigger slow background tasks (these are not interrupt-driven but polled).

"A" tasks are triggered at TASKA_FREQ, which is 100 Hz. The SFRA GUI must be called at this rate. One task, A1, is executed at this rate.

"B" tasks are triggered at TASKB_FREQ, which is 10 Hz. These are used for some basic LED toggles and state machine items that are not timing-critical. Three tasks—B1, B2, B3—are serviced by this; hence, each has an execution rate of 3.33 Hz.

#define TASKA_FREQ 100
#define TASKB_FREQ 10

The software of this reference design is organized into labs separated by solution, each with incremental builds (INCR_BUILD). These tests simplify the system bring up and design.

CLLLC Labs

Lab 1: Primary to Secondary Power Flow, Open Loop Check PWM driver, no high power applied to the board. See Section 5.2.2.1

Lab 2: Primary to Secondary Power Flow, Open Loop Check PWM driver and ADC with protection, resistive load connected on secondary. See Section 5.2.2.2.

Lab 3: Primary to Secondary Power Flow, Closed Voltage Loop Check, with resistive load connected on secondary. See Section 5.2.2.3.

Lab 4: Primary to Secondary Power Flow, Closed Current Loop Check, with resistive load connected on secondary. See Section 5.2.2.4.

Lab 5: Primary to Secondary Power Flow, Closed Current Loop Check, with resistive load connected on secondary in parallel to a voltage source to emulate a battery connection on secondary side. See Section 5.2.2.5.

These defines are in the "settings.h" file, and can be changed directly within that file.