TIDUF18A October 2022 – February 2024
The DC bus regulation loop is assumed to provide the power reference. The power reference is then divided by the square of the line voltage's RMS to provide the conductance, which is further multiplied by the line voltage giving the instantaneous current command.
Small signal model of the DC bus regulation loop is developed by linearizing Equation 9 around the operating point.
For a resistive load, the bus voltage and current are related as shown in Equation 10:
The DC voltage regulation loop control model can be drawn as shown in Figure 3-7. An additional Vbus feed forward is applied to make the control loop independent of the bus voltage. Therefore, the plant model for the bus control can be written as in Equation 11:
Using Figure 3-7, a proportional integrator (PI) compensator is designed for the voltage loop. The bandwidth of this loop is kept low as it is in conflict with the THD under steady state.