Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-6.5Gbps
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- TSW14J50 User's Guide (Rev. A)
(PDF 1531 KB)
25 Apr 2016
The Texas Instruments TSW14J50 Evaluation Module (EVM) is a next generation of pattern generator and data capture card used to evaluate performances of the Texas Instruments (TI) JESD204B family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC).
Populated with a low cost Altera Arria V GX device and using Altera’s JESD204B IP solution, the TSW14J50 can be dynamically configurable to support all lanes speeds from 600Mbps to 6.5Gbps, from 1 to 8 lanes, multiple converters, and multiple octets per frame.
Together with the accompanying High Speed Data Converter Pro Graphic User Interface (HSDC Pro GUI), it is a complete system that captures and evaluates data samples from ADC EVM’s and generates and sends desired test patterns to DAC EVM’s.
For 12.5Gbps JESD204B and 8Gb DDR3 SDRAM, please see TSW14J56EVM.
- Quickly evaluate JESD204B DAC and ADC performance using TI High Speed Data Converter Pro software
- Direct connection to all TI JESD204B High Speed Data Converter EVM’s using an FMC standard connector
- Quarter rate DDR3 controllers supporting up to 667MHz DDR3 operation
- JESD RX and TX IP cores with 8 routed transceiver channels
- Many available general purpose IO’s (status signals, SPI interface, etc.) between the FPGA and the FMC connector
- SPI/JTAG reconfigurable JESD core parameters: L,M,K,F,HD,S etc.
- Support for SUBCLASS 0 and 1 operation
- Dynamically reconfigurable transceiver data rate using HSDC Pro software
- Operating range from 0.611Gbps to 6.5Gbps
- 4Gb DDR3 SDRAM. Capture or send up to 256M 16 bit samples