The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed to sample input signals of up to 1.3 GHz.
The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very-low power consumption. On-chip dither provides an very-clean noise floor. Embedded foreground and background calibration provides consistent performance over the temperature range, and minimizes part-to-part variation.
This device supports the JESD204B serial interface with data rates up to 5 Gbps on each of two lanes, enabling high system integration density.
The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.
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|Part number||Order||Sample rate (Max) (MSPS)||Features||Resolution (Bits)||Number of input channels||SNR (dB)||ENOB (Bits)||SFDR (dB)||Power consumption (Typ) (mW)||Input range (Vp-p)||Interface||Operating temperature range (C)||Analog input BW (MHz)||Input buffer||Package Group||Package size: mm2:W x L (PKG)||Rating||Architecture|
||500||High Performance||16||1||70.6||11.3||83||915||1.7||JESD204B||-40 to 85||1300||Yes||WQFN | 40||40WQFN: 36 mm2: 6 x 6 (WQFN | 40)||Catalog||Pipeline|