ADS4249 Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC) | TI.com

ADS4249 (ACTIVE)

Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC) - ADS4249
Datasheet
ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC datasheet (Rev. E)
 

Description

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

Features

  • Maximum Sample Rate: 250 MSPS
  • Ultra-Low Power with Single 1.8-V Supply:
    • 560-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80-dBc SFDR at 170 MHz
    • 71.7-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with
      Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
    Lead (QFN) Package

Parametrics

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Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS4249 Order now 250     Low Power     14     2     72.8     11.7     80     470     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4222 Order now 65     Low Power     12     2     70.9     11.5     91     183     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4225 Order now 125     Low Power     12     2     70.8     11.5     89     277     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4226 Order now 160     Low Power     12     2     70.5     11.4     87     332     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4229 Order now 250     Low Power     12     2     70.5     11.3     80     470     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64