ADS62C17 Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC) |

This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC) - ADS62C17


ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range (–40°C to 85°C).


  • Maximum Sample Rate: 200 MSPS
  • 11-bit Resolution with No Missing Codes
  • 90 dBc SFDR at Fin = 10 MHz
  • 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
    using TI proprietary SNRBoost technology
  • Total Power 1.1 W at 200 MSPS
  • 90 dB Cross-talk
  • Double Data Rate (DDR) LVDS and Parallel
    CMOS Output Options
  • Programmable Gain up to 6dB for SNR/SFDR Trade-off
  • DC Offset Correction
  • Gain Tuning Capability in Fine Steps (0.001 dB)
    Allows Channel-to-channel Gain Matching
  • Supports Input Clock Amplitude Down to
    400 mV p-p Differential
  • Internal and External Reference Support
  • 64-QFN Package (9 mm × 9 mm)


Compare all products in High-speed ADCs (>10MSPS) Email Download to Excel
Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS62C17 Order now 200     High Performance     11     2     67     10.8     85     1081     2     Parallel LVDS     -40 to 85     700     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62C15 Samples not available 125     High Performance     11     2     67.2     10.8     89     740     2     Serial LVDS     -40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline