SBAS661C February   2015  – May 2021 ADS1262 , ADS1263

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Offset Temperature Drift Measurement
    2. 8.2 Gain Temperature Drift Measurement
    3. 8.3 Common-Mode Rejection Ratio Measurement
    4. 8.4 Power-Supply Rejection Ratio Measurement
    5. 8.5 Crosstalk Measurement (ADS1263)
    6. 8.6 Reference-Voltage Temperature-Drift Measurement
    7. 8.7 Reference-Voltage Thermal-Hysteresis Measurement
    8. 8.8 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multifunction Analog Inputs
      2. 9.3.2  Analog Input Description
        1. 9.3.2.1 ESD Diode
        2. 9.3.2.2 Input Multiplexer
      3. 9.3.3  Sensor Bias
      4. 9.3.4  Temperature Sensor
      5. 9.3.5  Power-Supply Monitor
      6. 9.3.6  PGA
      7. 9.3.7  PGA Voltage Overrange Monitors
        1. 9.3.7.1 PGA Differential Output Monitor
        2. 9.3.7.2 PGA Absolute Output-Voltage Monitor
      8. 9.3.8  ADC Reference Voltage
        1. 9.3.8.1 Internal Reference
        2. 9.3.8.2 External Reference
        3. 9.3.8.3 Power-Supply Reference
        4. 9.3.8.4 Low-Reference Monitor
      9. 9.3.9  ADC1 Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter Mode
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
        3. 9.3.10.3 50-Hz and 60-Hz Line Cycle Rejection
      11. 9.3.11 Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      12. 9.3.12 Level-Shift Voltage
      13. 9.3.13 General-Purpose Input/Output (GPIO)
      14. 9.3.14 Test DAC (TDAC)
      15. 9.3.15 ADC2 (ADS1263)
        1. 9.3.15.1 ADC2 Inputs
        2. 9.3.15.2 ADC2 PGA
        3. 9.3.15.3 ADC2 Reference
        4. 9.3.15.4 ADC2 Modulator
        5. 9.3.15.5 ADC2 Digital Filter
    4. 9.4 Device Functional Modes
      1. 9.4.1  Conversion Control
        1. 9.4.1.1 Continuous Conversion Mode
        2. 9.4.1.2 Pulse Conversion Mode
        3. 9.4.1.3 ADC2 Conversion Control (ADS1263)
      2. 9.4.2  Conversion Latency
      3. 9.4.3  Programmable Time Delay
      4. 9.4.4  Serial Interface
        1. 9.4.4.1 Chip Select (CS)
        2. 9.4.4.2 Serial Clock (SCLK)
        3. 9.4.4.3 Data Input (DIN)
        4. 9.4.4.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.4.4.5 Serial Interface Autoreset
      5. 9.4.5  Data Ready Pin (DRDY)
      6. 9.4.6  Conversion Data Software Polling
      7. 9.4.7  Read Conversion Data
        1. 9.4.7.1 Read Data Direct (ADC1 Only)
        2. 9.4.7.2 Read Data by Command
        3. 9.4.7.3 Data-Byte Sequence
          1. 9.4.7.3.1 Status Byte
          2. 9.4.7.3.2 Data Byte Format
          3. 9.4.7.3.3 Checksum Byte (CRC/CHK)
            1. 9.4.7.3.3.1 Checksum Mode (CRC[1:0] = 01h)
          4. 9.4.7.3.4 CRC Mode (CRC[1:0] = 10h)
      8. 9.4.8  ADC Clock Modes
        1. 9.4.8.1 Internal Oscillator
        2. 9.4.8.2 External Clock
        3. 9.4.8.3 Crystal Oscillator
      9. 9.4.9  Calibration
        1. 9.4.9.1 Offset and Full-Scale Calibration
          1. 9.4.9.1.1 Offset Calibration Registers
          2. 9.4.9.1.2 Full-Scale Calibration Registers
        2. 9.4.9.2 ADC1 Offset Self-Calibration (SFOCAL1)
        3. 9.4.9.3 ADC1 Offset System Calibration (SYOCAL1)
        4. 9.4.9.4 ADC2 Offset Self-Calibration ADC2 (SFOCAL2)
        5. 9.4.9.5 ADC2 Offset System Calibration ADC2 (SYOCAL2)
        6. 9.4.9.6 ADC1 Full-Scale System Calibration (SYGCAL1)
        7. 9.4.9.7 ADC2 Full-Scale System Calibration ADC2 (SYGCAL2)
        8. 9.4.9.8 Calibration Command Procedure
        9. 9.4.9.9 User Calibration Procedure
      10. 9.4.10 Reset
        1. 9.4.10.1 Power-On Reset (POR)
        2. 9.4.10.2 RESET/PWDN Pin
        3. 9.4.10.3 Reset by Command
      11. 9.4.11 Power-Down Mode
      12. 9.4.12 Chop Mode
    5. 9.5 Programming
      1. 9.5.1 NOP Command
      2. 9.5.2 RESET Command
      3. 9.5.3 START1, STOP1, START2, STOP2 Commands
      4. 9.5.4 RDATA1, RDATA2 Commands
      5. 9.5.5 SYOCAL1, SYGCAL1, SFOCAL1, SYOCAL2, SYGCAL2, SFOCAL2 Commands
      6. 9.5.6 RREG Command
      7. 9.5.7 WREG Command
    6. 9.6 Register Maps
      1. 9.6.1  Device Identification Register (address = 00h) [reset = x]
      2. 9.6.2  Power Register (address = 01h) [reset = 11h]
      3. 9.6.3  Interface Register (address = 02h) [reset = 05h]
      4. 9.6.4  Mode0 Register (address = 03h) [reset = 00h]
      5. 9.6.5  Mode1 Register (address = 04h) [reset = 80h]
      6. 9.6.6  Mode2 Register (address = 05h) [reset = 04h]
      7. 9.6.7  Input Multiplexer Register (address = 06h) [reset = 01h]
      8. 9.6.8  Offset Calibration Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration Registers (address = 0Ah, 0Bh, 0Ch) [reset = 40h, 00h, 00h]
      10. 9.6.10 IDACMUX Register (address = 0Dh) [reset = BBh]
      11. 9.6.11 IDACMAG Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 REFMUX Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 TDACP Control Register (address = 10h) [reset = 00h]
      14. 9.6.14 TDACN Control Register (address = 11h) [reset = 00h]
      15. 9.6.15 GPIO Connection Register (address = 12h) [reset = 00h]
      16. 9.6.16 GPIO Direction Register (address = 13h) [reset = 00h]
      17. 9.6.17 GPIO Data Register (address = 14h) [reset = 00h]
      18. 9.6.18 ADC2 Configuration Register (address = 15h) [reset = 00h]
      19. 9.6.19 ADC2 Input Multiplexer Register (address = 16h) [reset = 01h]
      20. 9.6.20 ADC2 Offset Calibration Registers (address = 17h, 18h) [reset = 00h, 00h]
      21. 9.6.21 ADC2 Full-Scale Calibration Registers (address = 19h, 1Ah) [reset = 00h, 40h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Isolated (or Floated) Inputs
      2. 10.1.2 Single-Ended Measurements
      3. 10.1.3 Differential Measurements
      4. 10.1.4 Input Range
      5. 10.1.5 Input Filtering
        1. 10.1.5.1 Aliasing
      6. 10.1.6 Input Overload
      7. 10.1.7 Unused Inputs and Outputs
      8. 10.1.8 Voltage Reference
      9. 10.1.9 Serial Interface Connections
    2. 10.2 Typical Application
      1. 10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.2 Conversion Latency

The digital filter averages and down-samples data from the modulator to provide the final data rate (rate reduction). The order of the digital filter affects the amount of data averaging and in turn, the time delay of the conversion (or filter latency). The FIR and sinc1 filter modes are zero latency providing the conversion result in single cycle. The higher order sinc filters (sinc2, 3, 4, 5) have more than one conversion latency and therefore require more conversion cycles to provide fully settled data. Tradeoffs can be made between 50-Hz and 60-Hz line cycle rejection verses conversion latency by selection of the sinc filter order. A higher order sinc filter increases the rejection of the 50-Hz and 60-Hz line cycles, but also increases the filter latency. Filter latency is an important consideration when multiplexing (scanning) through input channels. To make sure that conversions are settled after changing channels, start a new conversion for each channel using the START pin or start command. Note if the multiplexer is changed during ongoing conversions, the conversion is stopped and restarted at the time multiplexer register is changed.

Table 9-13 lists the filter latency after starting the first conversion. Note the conversion latency depends on the filter setting. The conversion latency is illustrated in Figure 9-39. Parameter td(STDR) shows the latency from start to conversion data ready (DRDY low). Note that settled data are provided, assuming the analog input is settled before the start condition. After the first conversion is completed (in continuous conversion mode), subsequent conversions occur at the nominal data rate. The latency values are for the programmable time-delay parameter set to off (DELAY[3:0] = 000).

GUID-164AD7DE-BD76-4E86-BD31-99C113C125C4-low.gifFigure 9-39 Conversion Latency After Start Condition
Table 9-13 ADC1 Conversion Latency, td(STDR)
DATA RATE
(SPS)		 CONVERSION LATENCY(1) (ms)
SINC1 SINC2 SINC3 SINC4 SINC5 FIR
2.5 400.4 800.4 1,200 1,600 — 402.2
5 200.4 400.4 600.4 800.4 — 202.2
10 100.4 200.4 300.4 400.4 — 102.2
16.6 60.35 120.4 180.4 240.4 — —
20 50.35 100.4 150.4 200.4 — 52.22
50 20.35 40.42 60.42 80.42 — —
60 17.02 33.76 50.42 67.09 — —
100 10.35 20.42 30.42 40.42 — —
400 2.855 5.424 7.924 10.42 — —
1200 1.188 2.091 2.924 3.758 — —
2400 0.771 1.258 1.674 2.091 — —
4800 0.563 0.8409 1.049 1.258 — —
7200 0.494 0.702 0.841 0.980 — —
14400 — — — — 0.424 —
19200 — — — — 0.337 —
38400 — — — — 0.207 —
(1) Chop and IDAC rotation off, DELAY[3:0] = 0000.

If using chop or IDAC rotation modes, the latency of the first conversion increases. The latency of chop and IDAC rotation modes is shown in Equation 19 and Equation 20.

Equation 19. Chop or IDAC rotation mode: latency = 2 · (td(STDR) + DELAY[3:0] value)
Equation 20. Chop and IDAC rotation modes: latency = 4 · (td(STDR) + DELAY[3:0] value)

In addition, chop or IDAC rotation mode can reduce the conversion data rate depending on the time-delay parameter. The 50-Hz and 60-Hz filter response nulls are not altered by chop or IDAC rotation modes. Equation 21 shows the effective data rate with the DELAY parameter.

Equation 21. Chop or IDAC rotation mode data rate = 1 / (td(STDR) + DELAY[3:0] value)

Table 9-14 shows the first conversion latency of ADC2. The filter latency is the elapsed time after sending the START2 command before the first conversion is ready.

Table 9-14 ADC2 Conversion Latency, td(STDR)
DATA RATE (SPS) CONVERSION LATENCY (ms)
10 121
100 31.2
400 8.71
800 4.97

If the input signal changes while the ADC is continuously converting, the output data are a mix of old and new data, as shown in Figure 9-40. The filter latency values for settled data (td(STDR)) with an input step change while continuously converting is shown in Table 9-15. The filter latency values listed in the table (td(STDR)) assume the analog input is settled before the start of the first whole conversion period.

GUID-FE9487BE-0128-4C66-8BD7-8B984EFA4F39-low.gifFigure 9-40 ADC1 Latency Timing While Continuously Converting
Table 9-15 Fully-Settled Conversion Values for Figure 9-40
DIGITAL FILTERFULLY SETTLED CONVERSION td(DRDR)
(1 / DR)(1)
FIR1
Sinc11
Sinc22
Sinc33
Sinc44
Sinc55
(1) Chop and IDAC rotation modes off.