SBAS813 June   2018 ADS8688AT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: Serial Interface
    7. 6.7 Switching Characteristics: Serial Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Overvoltage Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer (MUX)
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
      9. 7.3.9  Auxiliary Channel
        1. 7.3.9.1 Input Driver for the AUX Channel
      10. 7.3.10 ADC Transfer Function
      11. 7.3.11 Alarm Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface
        1. 7.4.1.1 Digital Pin Description
          1. 7.4.1.1.1 CS (Input)
          2. 7.4.1.1.2 SCLK (Input)
          3. 7.4.1.1.3 SDI (Input)
          4. 7.4.1.1.4 SDO (Output)
          5. 7.4.1.1.5 DAISY (Input)
          6. 7.4.1.1.6 RST/PD (Input)
        2. 7.4.1.2 Data Acquisition Example
        3. 7.4.1.3 Host-to-Device Connection Topologies
          1. 7.4.1.3.1 Daisy-Chain Topology
          2. 7.4.1.3.2 Star Topology
      2. 7.4.2 Device Modes
        1. 7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 7.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 7.4.2.3 STANDBY Mode (STDBY)
        4. 7.4.2.4 Power-Down Mode (PWR_DN)
        5. 7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
        6. 7.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 7.4.2.7 Channel Sequencing Modes
        8. 7.4.2.8 Reset Program Registers (RST)
    5. 7.5 Register Maps
      1. 7.5.1 Command Register Description
      2. 7.5.2 Program Register Description
        1. 7.5.2.1 Program Register Read/Write Operation
        2. 7.5.2.2 Program Register Map
        3. 7.5.2.3 Program Register Descriptions
          1. 7.5.2.3.1 Auto-Scan Sequencing Control Registers
            1. 7.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)
              1. Table 11. AUTO_SEQ_EN Field Descriptions
            2. 7.5.2.3.1.2 Channel Power Down Register (address = 02h)
              1. Table 12. Channel Power Down Register Field Descriptions
          2. 7.5.2.3.2 Device Features Selection Control Register (address = 03h)
            1. Table 13. Feature Select Register Field Descriptions
          3. 7.5.2.3.3 Range Select Registers (addresses 05h-0Ch)
            1. Table 16. Channel n Input Range Registers Field Descriptions
          4. 7.5.2.3.4 Alarm Flag Registers (Read-Only)
            1. 7.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)
              1. Table 17. ALARM Overview Tripped-Flag Register Field Descriptions
            2. 7.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
              1. Table 18. ALARM Ch0-3 Tripped-Flag Register Field Descriptions
              2. Table 19. ALARM Ch0-3 Active-Flag Register Field Descriptions
              3. Table 20. ALARM Ch4-7 Tripped-Flag Register Field Descriptions
              4. Table 21. ALARM Ch4-7 Active-Flag Register Field Descriptions
          5. 7.5.2.3.5 Alarm Threshold Setting Registers
            1. Table 22. Channel n Hysteresis Register Field Descriptions (n = 0 to 7)
            2. Table 23. Channel n High Threshold MSB Register Field Descriptions (n = 0 to 7)
            3. Table 24. Channel n High Threshold LSB Register Field Descriptions (n = 0 to 7)
            4. Table 25. Channel n Low Threshold MSB Register Field Descriptions (n = 0 to 7)
            5. Table 26. Channel n Low Threshold MSB Register Field Descriptions (n = 0 to 7)
          6. 7.5.2.3.6 Command Read-Back Register (address = 3Fh)
            1. Table 27. Command Read-Back Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2.3.5 Alarm Threshold Setting Registers

The ADS8688AT features individual high and low alarm threshold settings for each channel. Each alarm threshold is 16 bits wide with 8-bit hysteresis, which is the same for both high and low threshold settings. This 40-bit setting is accomplished through five 8-bit registers associated with every high and low alarm.

NAME ADDR REGISTER BITS
7 6 5 4 3 2 1 0
Ch 0 Hysteresis 15h CH0_HYST[7:0]
Ch 0 High Threshold MSB 16h CH0_HT[15:8]
Ch 0 High Threshold LSB 17h CH0_HT[7:0]
Ch 0 Low Threshold MSB 18h CH0_LT[15:8]
Ch 0 Low Threshold LSB 19h CH0_LT[7:0]
Ch 1 Hysteresis 1Ah CH1_HYST[7:0]
Ch 1 High Threshold MSB 1Bh CH1_HT[15:8]
Ch 1 High Threshold LSB 1Ch CH1_HT[7:0]
Ch 1 Low Threshold MSB 1Dh CH1_LT[15:8]
Ch 1 Low Threshold LSB 1Eh CH1_LT[7:0]
Ch 2 Hysteresis 1Fh CH2_HYST[7:0]
Ch 2 High Threshold MSB 20h CH2_HT[15:8]
Ch 2 High Threshold LSB 21h CH2_HT[7:0]
Ch 2 Low Threshold MSB 22h CH2_LT[15:8]
Ch 2 Low Threshold LSB 23h CH2_LT[7:0]
Ch 3 Hysteresis 24h CH3_HYST[7:0]
Ch 3 High Threshold MSB 25h CH3_HT[15:8]
Ch 3 High Threshold LSB 26h CH3_HT[7:0]
Ch 3 Low Threshold MSB 27h CH3_LT[15:8]
Ch 3 Low Threshold LSB 28h CH3_LT[7:0]
Ch 4 Hysteresis 29h CH4_HYST[7:0]
Ch 4 High Threshold MSB 2Ah CH4_HT[15:8]
Ch 4 High Threshold LSB 2Bh CH4_HT[7:0]
Ch 4 Low Threshold MSB 2Ch CH4_LT[15:8]
Ch 4 Low Threshold LSB 2Dh CH4_LT[7:0]
Ch 5 Hysteresis 2Eh CH5_HYST[7:0]
Ch 5 High Threshold MSB 2Fh CH5_HT[15:8]
Ch 5 High Threshold LSB 30h CH5_HT[7:0]
Ch 5 Low Threshold MSB 31h CH5_LT[15:8]
Ch 5 Low Threshold LSB 32h CH5_LT[7:0]
Ch 6 Hysteresis 33h CH6_HYST[7:0]
Ch 6 High Threshold MSB 34h CH6_HT[15:8]
Ch 6 High Threshold LSB 35h CH6_HT[7:0]
Ch 6 Low Threshold MSB 36h CH6_LT[15:8]
Ch 6 Low Threshold LSB 37h CH6_LT[7:0]
Ch 7 Hysteresis 38h CH7_HYST[7:0]
Ch 7 High Threshold MSB 39h CH7_HT[15:8]
Ch 7 High Threshold LSB 3Ah CH7_HT[7:0]
Ch 7 Low Threshold MSB 3Bh CH7_LT[15:8]
Ch 7 Low Threshold LSB 3Ch CH7_LT[7:0]
Figure 114. Ch n Hysteresis Registers
7 6 5 4 3 2 1 0
CHn_HYST[7:0]
R/W-0h

Table 22. Channel n Hysteresis Register Field Descriptions
(n = 0 to 7)

Bit Field Type Reset Description
7-0 Channel n Hysteresis[7-0] R/W 0h These bits set the channel high and low alarm hysteresis for channel n(n = 0 to 7)
For example, bits 7-0 of the channel 0 register (address 15h) set the channel 0 alarm hysteresis.

00000000 = No hysteresis

00000001 = ±1-LSB hysteresis

00000010 to 11111110 = ±2-LSB to ±254-LSB hysteresis

11111111 = ±255-LSB hysteresis
Figure 115. Ch n High Threshold MSB Registers
7 6 5 4 3 2 1 0
CHn_HT[15:8]
R/W-1h

Table 23. Channel n High Threshold MSB Register Field Descriptions
(n = 0 to 7)

Bit Field Type Reset Description
7-0 CHn_HT[15:8] R/W 1h These bits set the MSB byte for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 16h) set the MSB byte for the channel 0 high alarm threshold. The channel 0 high alarm threshold is AAFFh when bits 7-0 of the channel 0 high threshold MSB register (address 16h) are set to AAh and bits 7-0 of the channel 0 high threshold LSB register (address 17h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
Figure 116. Ch n High Threshold LSB Registers
7 6 5 4 3 2 1 0
CHn_HT[7:0]
R/W-1h

Table 24. Channel n High Threshold LSB Register Field Descriptions
(n = 0 to 7)

Bit Field Type Reset Description
7-0 CHn_HT[7-0] R/W 1h These bits set the LSB for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 17h) set the LSB for the channel 0 high alarm threshold. The channel 0 high alarm threshold is AAFFh when bits 7-0 of the channel 0 high threshold MSB register (address 16h) are set to AAh and bits 7-0 of the channel 0 high threshold LSB register (address 17h) are set to FFh.

0000 0000 = LSB byte is 00h

0000 0001 = LSB byte is 01h

0000 0010 to 1111 1110 = LSB byte is 02h to FEh

1111 1111 = LSB byte is FFh
Figure 117. Ch n Low Threshold MSB Registers
7 6 5 4 3 2 1 0
CHn_LT[15:8]
R/W-0h

Table 25. Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7)

Bit Field Type Reset Description
7-0 CHn_LT[15:8] R/W 0h These bits set the MSB byte for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 18h) set the MSB byte for the channel 0 low alarm threshold. The channel 0 low alarm threshold is AAFFh when bits 7-0 of the channel 0 low threshold MSB register (address 18h) are set to AAh and bits 7-0 of the channel 0 low threshold LSB register (address 19h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
Figure 118. Ch n Low Threshold LSB Registers
7 6 5 4 3 2 1 0
CHn_LT[7:0]
R/W-0h

Table 26. Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7)

Bit Field Type Reset Description
7-0 CHn_LT[7-0] R/W 00h These bits set the LSB for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 19h) set the LSB for the channel 0 low alarm threshold. The channel 0 low alarm threshold is AAFFh when bits 7-0 of the channel 0 low threshold MSB register (address 18h) are set to AAh and bits 7-0 of the channel 0 low threshold LSB register (address 19h) are set to FFh.

0000 0000 = LSB byte is 00h

0000 0001 = LSB byte is 01h

0000 0010 to 1110 1111 = LSB byte is 02h to FEh

1111 1111 = LSB byte is FFh