SBAS813 June   2018 ADS8688AT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: Serial Interface
    7. 6.7 Switching Characteristics: Serial Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Overvoltage Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer (MUX)
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
      9. 7.3.9  Auxiliary Channel
        1. 7.3.9.1 Input Driver for the AUX Channel
      10. 7.3.10 ADC Transfer Function
      11. 7.3.11 Alarm Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface
        1. 7.4.1.1 Digital Pin Description
          1. 7.4.1.1.1 CS (Input)
          2. 7.4.1.1.2 SCLK (Input)
          3. 7.4.1.1.3 SDI (Input)
          4. 7.4.1.1.4 SDO (Output)
          5. 7.4.1.1.5 DAISY (Input)
          6. 7.4.1.1.6 RST/PD (Input)
        2. 7.4.1.2 Data Acquisition Example
        3. 7.4.1.3 Host-to-Device Connection Topologies
          1. 7.4.1.3.1 Daisy-Chain Topology
          2. 7.4.1.3.2 Star Topology
      2. 7.4.2 Device Modes
        1. 7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 7.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 7.4.2.3 STANDBY Mode (STDBY)
        4. 7.4.2.4 Power-Down Mode (PWR_DN)
        5. 7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
        6. 7.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 7.4.2.7 Channel Sequencing Modes
        8. 7.4.2.8 Reset Program Registers (RST)
    5. 7.5 Register Maps
      1. 7.5.1 Command Register Description
      2. 7.5.2 Program Register Description
        1. 7.5.2.1 Program Register Read/Write Operation
        2. 7.5.2.2 Program Register Map
        3. 7.5.2.3 Program Register Descriptions
          1. 7.5.2.3.1 Auto-Scan Sequencing Control Registers
            1. 7.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)
              1. Table 11. AUTO_SEQ_EN Field Descriptions
            2. 7.5.2.3.1.2 Channel Power Down Register (address = 02h)
              1. Table 12. Channel Power Down Register Field Descriptions
          2. 7.5.2.3.2 Device Features Selection Control Register (address = 03h)
            1. Table 13. Feature Select Register Field Descriptions
          3. 7.5.2.3.3 Range Select Registers (addresses 05h-0Ch)
            1. Table 16. Channel n Input Range Registers Field Descriptions
          4. 7.5.2.3.4 Alarm Flag Registers (Read-Only)
            1. 7.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)
              1. Table 17. ALARM Overview Tripped-Flag Register Field Descriptions
            2. 7.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
              1. Table 18. ALARM Ch0-3 Tripped-Flag Register Field Descriptions
              2. Table 19. ALARM Ch0-3 Active-Flag Register Field Descriptions
              3. Table 20. ALARM Ch4-7 Tripped-Flag Register Field Descriptions
              4. Table 21. ALARM Ch4-7 Active-Flag Register Field Descriptions
          5. 7.5.2.3.5 Alarm Threshold Setting Registers
            1. Table 22. Channel n Hysteresis Register Field Descriptions (n = 0 to 7)
            2. Table 23. Channel n High Threshold MSB Register Field Descriptions (n = 0 to 7)
            3. Table 24. Channel n High Threshold LSB Register Field Descriptions (n = 0 to 7)
            4. Table 25. Channel n Low Threshold MSB Register Field Descriptions (n = 0 to 7)
            5. Table 26. Channel n Low Threshold MSB Register Field Descriptions (n = 0 to 7)
          6. 7.5.2.3.6 Command Read-Back Register (address = 3Fh)
            1. Table 27. Command Read-Back Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
ANALOG INPUTS
Full-scale input span(2)
(AIN_nP to AIN_nGND)		 Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF V A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF A
Input range = ±0.3125 × VREF –0.3125 × VREF 0.3125 × VREF A
Input range = ±0.15625 × VREF –0.15625 × VREF 0.15625 × VREF A
Input range = 2.5 × VREF 0 2.5 × VREF A
Input range = 1.25 × VREF 0 1.25 × VREF A
Input range = 0.625 × VREF 0 0.625 × VREF A
Input range = 0.3125 × VREF 0 0.3125 × VREF A
AIN_nP Operating input range,
positive input		 Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF V A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF A
Input range = ±0.3125 × VREF –0.3125 × VREF 0.3125 × VREF A
Input range = ±0.15625 × VREF –0.15625 × VREF 0.15625 × VREF A
Input range = 2.5 × VREF 0 2.5 × VREF A
Input range = 1.25 × VREF 0 1.25 × VREF A
Input range = 0.625 × VREF 0 0.625 × VREF A
Input range = 0.3125 × VREF 0 0.3125 × VREF A
AIN_nGND Operating input range,
negative input		 All input ranges –0.1 0 0.1 V B
zi Input impedance At TA = 25°C,
all input ranges		 0.85 1 1.15 MΩ B
Input impedance drift All input ranges 7 32 ppm/°C B
IIkg(in) Input leakage current With voltage at AIN_nP pin = VIN,
input range = ±2.5 × VREF 		VIN – 2.25
————
RIN 		µA A
With voltage at AIN_nP pin = VIN,
input range = ±1.25 × VREF 		VIN – 2.00
————
RIN 		A
With voltage at AIN_nP pin = VIN,
input ranges = ±0.625 × VREF; ±0.3125 × VREF; ±0.15625 × VREF 		VIN – 1.60
————
RIN 		A
With voltage at AIN_nP pin = VIN,
input range = 2.5 × VREF 		VIN – 2.50
————
RIN 		A
With voltage at AIN_nP pin = VIN,
input range = 1.25 × VREF; 0.625 × VREF; 0.3125 × VREF 		VIN – 2.50
————
RIN 		A
INPUT OVERVOLTAGE PROTECTION
VOVP Overvoltage protection voltage AVDD = 5 V –20 20 V B
AVDD = floating –11 11 B
SYSTEM PERFORMANCE
Resolution 16 Bits A
NMC No missing codes 16 Bits A
DNL Differential nonlinearity –0.99 ±0.5 1.5 LSB(3) A
INL Integral nonlinearity(6) –2 ±0.75 2 LSB A
EG Gain error At TA = 25°C, all input ranges ±0.02 ±0.05 %FSR(4) A
Gain error matching
(channel-to-channel)		 At TA = 25°C, all input ranges ±0.02 ±0.05 %FSR A
Gain error temperature drift All input ranges 1 6 ppm/°C B
EO Offset error At TA = 25°C,
input range = ±2.5 × VREF(10) 		±0.5 ±1 mV A
At TA = 25°C,
input range = ±1.25 × VREF 		±0.5 ±1 A
At TA = 25°C,
input range = ±0.625 × VREF 		±0.5 ±1.5 A
At TA = 25°C,
input range = ±0.3125 × VREF 		±0.5 ±1.5 A
At TA = 25°C,
input range = ±0.15625 × VREF 		±0.5 ±1.5 A
At TA = 25°C,
all unipolar input ranges		 ±0.5 ±2 A
Offset error matching
(channel-to-channel)		 At TA = 25°C,
input range = ±2.5 × VREF(10) 		±0.5 ±1 mV A
At TA = 25°C,
input range = ±1.25 × VREF 		±0.5 ±1 A
At TA = 25°C,
input range = ±0.625 × VREF 		±0.5 ±1.5 A
At TA = 25°C,
input range = ±0.3125 × VREF 		±0.5 ±1.5 A
At TA = 25°C,
input range = ±0.15625 × VREF 		±0.5 ±1.5 A
At TA = 25°C,
all unipolar input ranges		 ±0.5 ±2 A
Offset error temperature drift Input range = ±2.5 × VREF 1 15 ppm/°C B
Input range = ±1.25 × VREF 1 4 B
Input range = ±0.625 × VREF 1 4 B
Input range = ±0.3125 × VREF 2 15 B
Input range = ±0.15625 × VREF 4 26 B
Input range = 0 to 2.5 × VREF 1 12 B
Input range = 0 to 1.25 × VREF 1 6 B
Input range = 0 to 0.625 × VREF 2 15 B
Input range = 0 to 0.3125 × VREF 4 26 B
SAMPLING DYNAMICS
tCONV Conversion time 850 ns A
tACQ Acquisition time 1150 ns A
fS Maximum throughput rate
without latency		 500 kSPS A
DYNAMIC CHARACTERISTICS
SNR Signal-to-noise ratio
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±2.5 × VREF 90 92 dB A
Input range = ±1.25 × VREF 89 91 A
Input range = ±0.625 × VREF 87.5 89 A
Input range = ±0.3125 × VREF 81.5 83 A
Input range = ±0.15625 × VREF 75.5 77 A
Input range = 2.5 × VREF 88.5 90.5 A
Input range = 1.25 × VREF 87.5 89 A
Input range = 0.625 × VREF 81.5 83 A
Input range = 0.3125 × VREF 75.5 77 A
THD Total harmonic distortion(5)
(VIN – 0.5 dBFS at 1 kHz)		 Input ranges = ±2.5 × VREF, ±1.25 × VREF, ±0.625 × VREF, 2.5 × VREF, 1.25 × VREF –102 dB B
Input ranges = ±0.3125 × VREF, ±0.15625 × VREF, 0.625 × VREF, 0.3125 × VREF –100
SINAD Signal-to-noise ratio
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±2.5 × VREF 89 91.5 dB A
Input range = ±1.25 × VREF 88.5 91 A
Input range = ±0.625 × VREF 87 89 A
Input range = ±0.3125 × VREF 81 83 A
Input range = ±0.15625 × VREF 75 77 A
Input range = 2.5 × VREF 87.5 90.5 A
Input range = 1.25 × VREF 87 89 A
Input range = 0.625 × VREF 81 83 A
Input range = 0.3125 × VREF 75 77 A
SFDR Spurious-free dynamic range
(VIN – 0.5 dBFS at 1 kHz)		 Input ranges = ±2.5 × VREF, ±1.25 × VREF, ±0.625 × VREF, 2.5 × VREF, 1.25 × VREF 103 dB B
Input ranges = ±0.3125 × VREF, ±0.15625 × VREF, 0.625 × VREF, 0.3125 × VREF 101
Crosstalk isolation(7) Aggressor channel input overdriven to 2 × maximum input voltage 110 dB B
Crosstalk memory(8) Aggressor channel input overdriven to 2 × maximum input voltage 90 dB B
BW(–3 dB) Small-signal bandwidth, –3 dB At TA = 25°C, all input ranges 15 kHz B
BW(–0.1 dB) Small-signal bandwidth, –0.1 dB At TA = 25°C, all input ranges 2.5 kHz B
AUXILIARY CHANNEL
Resolution 16 Bits A
V(AUX_IN) AUX_IN voltage range (AUX_IN – AUX_GND) 0 VREF V A
Operating input range AUX_IN 0 VREF V A
AUX_GND 0 V A
Ci Input capacitance During sampling 75 pF C
During conversion 5 pF C
IIkg(in) Input leakage current 100 nA A
DNL Differential nonlinearity –0.99 ±0.6 2 LSB A
INL Integral nonlinearity –4 ±1.5 4 LSB A
EG(AUX) Gain error At TA = 25°C ±0.02 ±0.2 %FSR A
EO(AUX) Offset error At TA = 25°C –5 5 mV A
SNR Signal-to-noise ratio V(AUX_IN) = –0.5 dBFS at 1 kHz 87 89 dB A
THD Total harmonic distortion(5) V(AUX_IN) = –0.5 dBFS at 1 kHz –102 dB B
SINAD Signal-to-noise + distortion V(AUX_IN) = –0.5 dBFS at 1 kHz 86 88.5 dB A
SFDR Spurious-free dynamic range V(AUX_IN) = –0.5 dBFS at 1 kHz 103 dB B
INTERNAL REFERENCE OUTPUT
V(REFIO_INT)(9) Voltage on REFIO pin
(configured as output)		 At TA = 25°C 4.095 4.096 4.097 V A
Internal reference temperature drift 6 17 ppm/°C B
C(OUT_REFIO) Decoupling capacitor on REFIO 10 22 µF B
V(REFCAP) Reference voltage to ADC
(on REFCAP pin)		 At TA = 25°C 4.095 4.096 4.097 V A
Reference buffer output impedance 0.5 1 Ω B
Reference buffer temperature drift 0.6 4.5 ppm/°C B
C(OUT_REFCAP) Decoupling capacitor on REFCAP 10 22 μF B
Turn-on time C(OUT_REFCAP) = 22 µF,
C(OUT_REFIO) = 22 µF		 15 ms B
EXTERNAL REFERENCE INPUT
VREFIO_EXT External reference voltage on REFIO (configured as input) 4.046 4.096 4.146 V C
POWER-SUPPLY REQUIREMENTS
AVDD Analog power-supply voltage Analog supply 4.75 5 5.25 V B
DVDD Digital power-supply voltage Digital supply range 1.65 3.3 AVDD V B
Digital supply range for specified performance 2.7 3.3 5.25 B
IAVDD_DYN Analog supply current Dynamic, AVDD AVDD = 5 V, fS = maximum and internal reference 13 16 mA A
IAVDD_STC Static AVDD = 5 V, device not converting and internal reference 10 12 mA A
ISTDBY Standby At AVDD = 5 V, device in STDBY mode and internal reference 3 4.5 mA A
IPWR_DN Power-down At AVDD = 5 V, device in PWR_DN 3 20 μA B
IDVDD_DYN Digital supply current At DVDD = 3.3 V, output = 0000h 0.5 mA A
DIGITAL INPUTS (CMOS)
VIH Digital input high logic levels DVDD > 2.1 V 0.7 × DVDD DVDD + 0.3 V A
DVDD ≤ 2.1 V 0.8 × DVDD DVDD + 0.3 A
VIL Digital input low logic levels DVDD > 2.1 V –0.3 0.3 × DVDD V A
DVDD ≤ 2.1 V –0.3 0.2 × DVDD A
Input leakage current 100 nA A
Input pin capacitance 5 pF C
DIGITAL OUTPUTS (CMOS)
VOH Digital output logic levels IO = 500-μA source 0.8 × DVDD DVDD V A
VOL IO = 500-μA sink 0 0.2 × DVDD A
Floating state leakage current Only for SDO 1 µA A
Internal pin capacitance 5 pF C
(1) Test Levels: (A) Tested at final test. Overtemperature limits are set by characterization and simulation. (B) Limits set by characterization and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.
(2) Ideal input span, does not include gain or offset error.
(3) LSB = least significant bit.
(4) FSR = full-scale range.
(5) Calculated on the first nine harmonics of the input frequency.
(6) This parameter is the endpoint INL, not best-fit INL.
(7) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing sequence, and measuring its effect on the output of any selected channel.
(8) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel that is selected in the multiplexing sequence, and measuring its effect on the output of the next selected channel for all combinations of input channels.
(9) Does not include the variation in voltage resulting from solder-shift and long-term effects.
(10) Does not include the shift in offset over time.