DLPS037G October   2014  – November 2023 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics #GUID-A1639D57-2918-4D83-ADD0-B21B369F4B9B/DLPS0379327
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15-V System Power
        2. 8.1.1.2 1.8-V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5-V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.15 DMD LVDS Interface Switching Characteristics

Switching characteristics over recommended operating conditions (1) (2) (3) (4) (5) (6)
PARAMETERFROM (INPUT)TO (OUTPUT)MINMAXUNIT
ƒclockClock frequency, DCK_AN/ADCK_A100400MHz
tcCycle time, DCK_A1N/ADCK_A2475.3ps
tw(H)Pulse duration, high 5 (50% to 50% reference points)N/ADCK_A1093ps
tw(L)Pulse duration, low 5 (50% to 50% reference points)N/ADCK_A1093ps
ttTransition time, tt = tƒ / tr (20% to 80% reference points)N/ADCK_A100400ps
tosuOutput setup time at max clock rate3DCK_A↑↓SCA, DDA(15:0)438ps
tohOutput hold time at max clock rate3DCK_A↑↓SCA, DDA(15:0)438ps
ƒclockClock frequency, DCK_BN/ADCK_B100400MHz
tcCycle time, DCK_B1N/ADCK_B2475.3ps
tw(H)Pulse duration, high 5 (50% to 50% reference points)N/ADCK_B1093ps
tw(L)Pulse duration, low 5 (50% to 50% reference points)N/ADCK_B1093ps
ttTransition time, tt = tƒ / tr (20% to 80% reference points)N/ADCK_B100400ps
tosuOutput setup time at max clock rate3DCK_B↑↓SCB, DDB(15:0)438ps
tohOutput hold time at max clock rate3DCK_B↑↓SCB, DDB(15:0)438ps
tskOutput skew, channel A to channel BDCK_A↑DCK_B↑250ps
(1) The minimum cycle time (tc) for DCK_A and DCK_B includes 1.0% spread spectrum modulation.
(2) The DMD LVDS interface uses a double data rate (DDR) clock, thus both rising and falling edges of DCK_A and DCK_B are used to clock data into the DMD. As a result, the minimum tw(H) and tw(L) parameters determine the worse-case DDR clock cycle time.
(3) Output setup and hold times for DMD clock frequencies below the maximum can be calculated as follows:
tosu(ƒclock) = tosu(ƒmax) + 250000 × (1 / ƒclock – 1 / 400) and toh(ƒclock) = toh(ƒmax) + 250000 × (1 / ƒclock – 1 / 400) where ƒclock is in MHz.
(4) The DLPC900 is a Full-Bus DMD signaling interface. Figure 6-4 shows the controller connections for this configuration.
(5) The pulse duration minimum for any clock rate can be calculated using the following formulas.
  1. Pulse duration minimum when using spread spectrum
    1. Duty cycle % = 49.06 – [0.01335 × clock frequency (MHz)]
    2. Minimum pulse duration = 1 / clock frequency × DC%
      1. Example: At 400 MHz: DC% = 49.06 – [0.01335 × 400] = 43.72%
      2. MPW = 1 / 400 MHz × 0.4372 = 1093.0 ps
  2. Pulse duration minimum when not using spread spectrum
    1. Duty cycle % = 49.00 – [0.01055 × clock frequency (MHz)]
    2. Minimum pulse duration = 1 / clock frequency × DC%
      1. Example: At 400 MHz: DC% = 49.00 – [0.01055 × 400] = 44.78%
      2. MPW = 1 / 400 MHz × 0.448 = 1119.5 ps
(6) A duty cycle specification is not provided because the key limiting factor to clock frequency is the minimum pulse duration (that is, if the other half of the clock period is larger than the minimum, it is not limiting the clock frequency).
GUID-20230412-SS0I-KQDK-HXWV-2NG9XLDGWG31-low.svg Figure 5-13 DMD LVDS Interface