DLPS037F October 2014 – June 2021 DLPC900
Although the DLPC900 requires an array of power supply voltages, for example, 1.15 V, 1.8 V, and 3.3 V, there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC900, as long as the system is held in reset during power supply sequencing. This is true for both power-up (reset controlled by POSENSE) and power-down (reset controlled by PWRGOOD) scenarios. Similarly, there is no minimum time between powering-up or powering-down the different supplies feeding the DLPC900. However, power-sequencing requirements are common for the devices that share the supplies with the DLPC900.
Power-sequencing recommendations to ensure proper operation are:
It is assumed that all DLPC900 power-up sequencing
is handled by external hardware. It is also assumed that an external power monitor
will hold the DLPC900 in system reset during power-up (that is, POSENSE = 0). During
this time all controller I/O's will be tri-stated. The primary PLL (PLLM1) will be
released from reset upon the low-to-high transition of POSENSE, but the DLPC900 will
be kept in reset for an additional 60 ms to allow the PLL to lock and stabilize its
outputs. After this delay the DLPC900 internal resets will be deasserted, thus
causing the processor to begin its boot-up routine.
Figure 9-2 shows the recommended DLPC900 system power-up sequence of the regulators: