DLPS037F October   2014  – June 2021 DLPC900

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements (1)
    7. 6.7  Power-Up and Power-Down Timing Requirements
      1. 6.7.1 Power-Up
      2. 6.7.2 Power-Down
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 6.10 Programmable Output Clocks Switching Characteristics
    11. 6.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 6.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 6.13 SSP Switching Characteristics
    14. 6.14 DMD Interface Switching Characteristics (1)
    15. 6.15 DMD LVDS Interface Switching Characteristics
    16. 6.16 Source Input Blanking Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DMD Configurations
      2. 7.3.2 Video Timing Input Blanking Specification
      3. 7.3.3 Board-Level Test Support
      4. 7.3.4 Two Controller Considerations
      5. 7.3.5 Memory Design Considerations
        1. 7.3.5.1 Flash Memory Optimization
        2. 7.3.5.2 Operating Modes
        3. 7.3.5.3 DLPC900 Memory Space
        4. 7.3.5.4 Minimizing Memory Space
        5. 7.3.5.5 Minimizing Board Size
          1. 7.3.5.5.1 Package Selection
          2. 7.3.5.5.2 Large Density Flash
            1. 7.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
              1. 7.3.5.5.2.1.1 Combining Three Chip-Selects with One 64-Megabyte Flash
            2. 7.3.5.5.2.2 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 7.3.5.6 Minimizing Board Space
        7. 7.3.5.7 Flash Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 Structured Light Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Two Controller Chipset
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 DLPC900 System Interfaces
            1. 8.2.1.2.1.1 Control Interface
            2. 8.2.1.2.1.2 Input Data Interfaces
            3. 8.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 8.2.1.2.1.3.1 Illumination Interface
              2. 8.2.1.2.1.3.2 Trigger and Sync Interface
            4. 8.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 8.2.1.2.1.4.1 Reference Clock and PLL
              2. 8.2.1.2.1.4.2 Program Memory Flash Interface
              3. 8.2.1.2.1.4.3 DMD Interface
      2. 8.2.2 Typical Single Controller Chipset
  9. Power Supply Recommendations
    1. 9.1 System Power Regulation
      1. 9.1.1 Power Distribution System
        1. 9.1.1.1 1.15-V System Power
        2. 9.1.1.2 1.8-V System Power
        3. 9.1.1.3 3.3-V System Power
    2. 9.2 System Environment and Defaults
      1. 9.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 9.3 System Power-Up Sequence
      1. 9.3.1 Power-On Sense (POSENSE) Support
      2. 9.3.2 Power Good (PWRGOOD) Support
      3. 9.3.3 5-V Tolerant Support
    4. 9.4 System Reset Operation
      1. 9.4.1 Power-Up Reset Operation
      2. 9.4.2 System Reset Operation
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General PCB Recommendations
      2. 10.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 10.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 10.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 10.1.5  Spread Spectrum Clock Generator Support
      6. 10.1.6  GPIO Interface
      7. 10.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 10.1.8  DMD Interface Considerations
        1. 10.1.8.1 Flex Connector Plating
      9. 10.1.9  PCB Design Standards
      10. 10.1.10 Signal Layers
      11. 10.1.11 Trace Widths and Minimum Spacing
      12. 10.1.12 Trace Impedance and Routing Priority
      13. 10.1.13 Power and Ground Planes
      14. 10.1.14 Power Vias
      15. 10.1.15 Decoupling
      16. 10.1.16 Fiducials
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
      3. 11.1.3 DEFINITIONS - Video Timing Parameters
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Example

The DLP® LightCrafter™ Dual DLPC900 Evaluation Module (EVM) PCB is targeted at 14 layers with layer stack up shown in Figure 10-7. The PCB layer stack can vary depending on system design. However, careful attention is required to meet design considerations. Layers 1 and 14 consist of the component layers. Layers 2, 4, 6, 9, 11, and 13 consist of solid ground planes. Layers 7 and 8 consist of solid power planes. Layers 1, 3, 5, 10, 12, and 14 are used as the primary routing layers. Routing on external layers must be less than 0.25 inches for priority one and two signals. Refer to the Table 10-9 for signal priority groups. Board material must be FR-370HR or similar. PCB must be designed for lead-free assembly with the stackup geometry shown in Figure 10-7 and Figure 10-8.

GUID-61328606-4358-4D29-B8C5-938590DEAE1F-low.gifFigure 10-7 Board Layer Stack
GUID-A0886EE0-A5EE-4457-85BC-043E74B02244-low.gifFigure 10-8 Board Trace Geometry

Refer to Section 10.2 for a complete set of documentation for the DLP® LightCrafter™ Dual DLPC900 Evaluation Module (EVM) reference design.