DLPS037G October   2014  – November 2023 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics #GUID-A1639D57-2918-4D83-ADD0-B21B369F4B9B/DLPS0379327
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15-V System Power
        2. 8.1.1.2 1.8-V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5-V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5.3 DLPC900 External Memory Space

The external memory space of the DLPC900 consists of three chip-selects:

  1. CS0
  2. CS1—Power-up boot chip select
  3. CS2

The DLPC900 is capable of accessing up to 16-megabytes of memory on each chip-select plus two optional GPIOs for extended external memory access (GPIO_45, GPIO_46). CS1 contains the firmware, and it is the power-up boot chip-select.

The memory space shown in Figure 6-6 displays how the DLPC900 accesses the memory when memory is present on all three chip selects. Although the chip-selects are numbered 0, 1, and 2, the way the DLPC900 accesses the memory is not in this order. Notice that the boot flash is located on chip select CS1.

GUID-1FA4346B-8537-4971-9CEB-A80FCFBDEC9C-low.gif Figure 6-6 DLPC900 Memory Space

During the power-up initialization, the DLPC900 firmware performs a query on each chip-select to determine whether there is memory present. If there is no memory present on CS1, then the DLPC900 will not boot up; therefore, flash memory and the firmware must exist on CS1.

Note that the addresses from CS2 to CS0 are not ascending linearly in Figure 6-6; therefore, an image cannot span across CS2 and CS0. If an image cannot entirely fit in CS2, then the entire image must be moved and stored in CS0.

If more memory space is required, the DLPC900 memory space can also be organized into a single flash memory device larger than 48 megabytes. By using the architecture shown in Figure 6-7, a flash memory device up to 128 megabytes can be attached to the DLPC900. Table 6-2 describes the memory space layout of a 128-megabyte flash device. Similar to memories attached directly to chip selects, an image also cannot span across memory blocks when using a single large flash memory with the DLPC900.

GUID-20201208-CA0I-5DTK-MLVD-ZJQZW75L6GQL-low.svgFigure 6-7 One 128-Megabyte Flash Device
Table 6-2 Flash Device Layout
MEMORY BLOCKADDRESS SPACE (START AND END)SINGLE FLASH MEMORY ADDRESSEDMEGABYTESCONTENTS
00xF9000000 - 0xF901FFFF 0x00000000 - 0x0001FFFF0 - 0.128 Bootloader
0xF9020000 - 0xF913FFFF0x00020000 - 0x0013FFFF0.128 - 1.15Application binary, Sequences / Patterns
0xF9140000 - 0xF923FFFF0x00140000 - 0x0023FFFF1.15 - 2.15Reserved space
0xF9240000 - 0xF9FFFFFF0x00240000 - 0x00FFFFFF2.15 - 15

Patterns only

10xFA000000 - 0xFAFFFFFF0x01000000 - 0x01FFFFFF16 - 31Patterns only
20xF8000000 - 0xF8FFFFFF 0x02000000 - 0x02FFFFFF32 - 47Patterns only
30x03000000 - 0x03FFFFFF0x03000000 - 0x03FFFFFF48 - 63Patterns only
40x04000000 - 0x04FFFFFF0x04000000 - 0x04FFFFFF64 - 79Patterns only
50x05000000 - 0x05FFFFFF0x05000000 - 0x05FFFFFF80 - 95Patterns only
60x06000000 - 0x06FFFFFF0x06000000 - 0x06FFFFFF96 - 111Patterns only
70x07000000 - 0x07FFFFFF0x07000000 - 0x07FFFFFF112 - 127Patterns only

The design for a single 128-megabyte flash device for storing the firmware consists of the bootloader, the main application, sequences/images stored in flash (optional), and 1-megabyte of reserved space. The bootloader is located at the beginning of the flash memory block 0. The size of the bootloader is 128-kilobytes, beginning at address 0xF9000000. The bootloader is necessary for operation. If the bootloader becomes corrupted in some way it can render the device inoperable. The bootloader is followed by the main application and then sequence/image data. As mentioned above, patterns must not span memory block boundaries. If a pattern does not fit in a given block, the entire 24-bit image (or composite image) must be moved in the next block. Additionally, the 1-megabyte of reserved space in memory block 0 from 0xF9140000 to 0xF923FFFF is necessary for operation and must not be overwritten.