DLPS037F October 2014 – June 2021 DLPC900
A typical embedded system application using the DLPC900 controller and DLP9000, DLP500YX, or DLP670S DMD is shown in Figure 8-1. This configuration requires two DLPC900 controllers to drive a DLP9000, DLP500YX, or DLP670S DMD and supports a 24-bit parallel RGB input, typical of LCD interfaces, from an external source or processor. In this configuration, the 24-bit parallel RGB input data is split between the primary and the secondary controller as described in Section 7.3.4 using an FPGA or some other mechanism.
This system supports both still and motion video sources with the input resolution native to the DLP9000, DLP500YX, or DLP670S DMD. However, the controller supports only sources with periodic synchronization pulses. This support is ideal for motion video sources, but can also be used for still images by maintaining periodic syncs and sending a new frame of data only when needed. The still image must be fully contained within a single video frame and meet the frame timing constraints. The DLPC900 controller refreshes the displayed image at the source frame rate and repeats the last active frame for intervals in which no new frame has been received.
This configuration also supports the high-speed sequential pattern modes mentioned in the Section 7.4.1. The patterns can be from the video source, from the USB or I2C interface, or pre-stored in external flash, and have a maximum of 24 bits per pixel. The patterns are pre-loaded into the internal embedded DRAM and then streamed to the DLP9000, DLP500YX, or DLP670S DMD at high speeds.