DLPS037G October   2014  – November 2023 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics #GUID-A1639D57-2918-4D83-ADD0-B21B369F4B9B/DLPS0379327
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15-V System Power
        2. 8.1.1.2 1.8-V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5-V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.1 Structured Light Application

For structured light applications, the DLPC900 can be commanded to enter the following high speed sequential pattern modes.

  1. Video Pattern Mode
  2. Pre-Stored Pattern Mode
  3. Pattern On-The-Fly Mode
In each mode a specific set of patterns are selected with a maximum of 24 bits per pixel. The bit-depth of the patterns are then allocated into the corresponding time slots. Furthermore, an output trigger signal is also synchronized with these time slots to indicate when the image is displayed.

These pattern modes provide the capability to display a set of patterns and signal a camera to capture these patterns overlaid on an object. The DLPC900 controller is capable of preloading up to 400 1-bit binary patterns or 960 1-bit binary patterns for the DLP5500 into internal memory from the external flash memory or from the USB or I2C interfaces. These preloaded binary patterns are then streamed to the DMD at high speed.

Note:

When using Pre-Stored Pattern Mode, the number of patterns that can be stored in External Flash depends on the size of the external flash and level of compression achievable.

Table 6-3 Number of 1-Bit Pre-Stored Patterns for Each DMD
DMD Number of Patterns
DLP5500 960
DLP500YX 400
DLP6500 400
DLP670S 400
DLP9000 400

The DLPC900 controller is capable of synchronizing a camera to the displayed patterns. In video pattern mode, the vertical sync is used as trigger input. In pre-stored pattern mode and pattern on-the-fly mode, an internal user configurable trigger or a TRIG_IN_1 pulse indicates to the DLPC900 controller to advance to the next pattern, while TRIG_IN_2 starts and stops the pattern sequence. In all pattern modes, TRIG_OUT_1 frames the exposure time of the pattern, while TRIG_OUT_2 indicates the start of the pattern sequence.

Figure 6-16 shows an example timing diagram of video pattern mode. The VSYNC starts the pattern sequence display. The pattern sequence consists of a series of four patterns followed by a series of three patterns and then repeats. The first pattern sequence consists of P1, P2, P3, and P4. The second pattern sequence consists of P5, P6, and P7. TRIG_OUT_1 frames each pattern exposed, while TRIG_OUT_2 indicates the start of each pattern in the sequence. If the pattern sequence is configured without dark time between patterns, then the TRIG_OUT_1 output would be high for the entire pattern sequence.

GUID-FF339EDE-BC0C-4CEB-8DB1-846C444A5CDA-low.gif Figure 6-16 Video Pattern Mode Timing Diagram

Figure 6-17 shows an example of a prestored pattern mode timing diagram. Pattern sequences of four are displayed. TRIG_OUT_1 frames each pattern exposed, while TRIG_OUT_2 indicates the start of each pattern in the sequence. If the pattern sequence is configured without dark time between patterns, then the TRIG_OUT_1 output would be high for the entire pattern sequence.

GUID-E8E28684-31B8-426B-82AF-8E9ACA376EB0-low.gif Figure 6-17 Pre-Stored Pattern Mode Timing Diagram

Another example of a prestored pattern mode timing diagram is shown in Figure 6-18, where pattern sequences of three are displayed. TRIG_OUT_1 frames each pattern displayed, while TRIG_OUT_2 indicates the start of each pattern. TRIG_IN_2 serves as a start and stop signal. When high, the pattern sequence starts or continues. Note, in the middle of displaying the P4 pattern, TRIG_IN_2 is low, so the sequence stops displaying P4. When TRIG_IN_2 is raised, the pattern sequence continues where it stopped by re-displaying P4.

GUID-2661CECD-6BBC-4129-8E0B-F904B4E0F143-low.gif Figure 6-18 Pre-Stored Pattern Mode Timing Diagram for 3-Patterns

Table 6-4 shows the allowed pattern combinations in relation to the bit depth of the pattern. If the pattern sequence is configured without dark time between patterns, then the TRIG_OUT_1 output would be high for the entire pattern sequence. For faster 8-bit pattern speeds, the illumination source can be modulated to shorten the smallest bits, and thus the larger bits. This method will introduce dark time into the pattern and affect the brightness, but it is capable of 8-bit pattern speeds up to four times faster than patterns without illumination modulation. More information on illumination modulation can be found in the DLP® LightCrafter™ Single DLPC900 Evaluation Module (EVM) User's Guide or DLP® LightCrafter™ Dual DLPC900 Evaluation Module (EVM) User's Guide.

Table 6-4 Minimum Pattern Time in Any Pattern Mode
BIT DEPTH DLP5500 (µs) DLP6500 (µs) DLP9000 (µs) DLP500YX (µs) DLP670S (µs)
1 94 105 105 62 100
2 275 304 304 184 343
3 365 394 380 269 438
4 444 823 733 458 768
5 972 1215 1215 682 1299
6 1512 1487 1487 807 1488
7 1877 1998 1998 1083 2000
8 3753 4046 4046 2263 4046
8(3) N/A 969 969 496 969
(3) Minimum achievable exposure using smallest allowed Minimum LED Pulse Width
Table 6-5 shows the minimum pattern time for a 1-bit pattern in relation to the number of active DMD blocks.
Table 6-5 Minimum Exposures for Number of Active DMD Blocks
ACTIVE BLOCKS DLP5500 (µs) DLP6500 (µs) DLP9000 (µs) DLP500YX (µs) DLP670S (µs)
1 25 (1) 24 24 30 27
2 30 (1) 45 42 30 27
3 35 (1) 45 42 30 27
4 28 45 42 30 33
5 33 48 45 34 38
6 38 54 51 38 38
7 43 60 56 42 49
8 48 66 61 46 55
9 53 72 67 50 61
10 58 78 72 54 66
11 63 84 77 58 72
12 68 90 83 62 77
13 73 96 88 N/A 83
14 78 101 93 N/A 89
15 83 105 99 N/A 94
16 94 N/A 105 N/A 100
(1) To accommodate the 20-μs trigger pulse and 5.2-μs block reset time, minimum exposure times for active blocks 1, 2, and 3 are calculated differently than the following active blocks.