DLPS037G October   2014  – November 2023 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics #GUID-A1639D57-2918-4D83-ADD0-B21B369F4B9B/DLPS0379327
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15-V System Power
        2. 8.1.1.2 1.8-V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5-V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-5FAF42BE-E849-47DD-A7F6-A9767DFA6AE4-low.gifFigure 4-1 ZPC Package 516-Pin BGA Bottom View
Table 4-1 Initialization Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
POSENSE P22 VDD33 I4
H		 Async Power-On Sense is an active high signal with hysteresis, generated from an external voltage monitor circuit. This signal is driven active high when all the controller supply voltages have reached 90% of their specified minimum voltage. This signal is driven inactive low after the falling edge of PWRGOOD as shown in Figure 5-4 and Figure 5-5. Refer to Section 5.7 for more details.
PWRGOOD T26 VDD33 I4
H		 Async Power Good is an active high signal with hysteresis that is provided from an external voltage monitor circuit. A high value indicates all power is within operating voltage specifications and the system is safe to exit its RESET state. Refer to Section 5.7 for more details.
EXT_ARSTZ T24 VDD33 O2 Async General purpose active low reset output signal. This output is driven low immediately after POSENSE is externally driven low, placing the system in RESET and remains low while POSENSE remains low. EXT_ARSTZ will continue to be held low after POSENSE is driven high and released by the controller firmware. EXT_ARSTZ is also driven low approximately 5 µs after the detection of a PWRGOOD or any internally generated reset. In all cases, it will remain active for a minimum of 2 ms.
CTRL_ARSTZ T25 VDD33 O2 Async Controller active low reset output signal. This output is driven low immediately after POSENSE is externally driven low and remains low while POSENSE remains low. CTRL_ARSTZ will continue to be held low after POSENSE is driven high and released by the controller firmware. CTRL_ARSTZ is also optionally asserted low approximately 5 µs after the detection of a PWRGOOD or any internally generated reset. In all cases it will remain active for a minimum of 2 ms.
AFE_ARSTZ AC12 VDD33 O2 Async Analog Front End active low reset output signal. This output is driven low immediately upon asserting power-up reset (POSENSE) low and remains low while POSENSE remains low. AFE_ARSTZ continues to be held low after the release of power-up reset (that is, POSENSE set high) until released by software. AFE_ARSTZ is also asserted low approximately 5 µs after the detection of a PWRGOOD or any internally generated reset. In all cases, it remains active for a minimum of 2 ms after the reset condition is released by software. Note that the ASIC contains a software register that can be used to independently drive this output. This pin requires an external 4.7-kΩ pullup resistor.
AFE_IRQ AB13 VDD33 I4 Async Analog Front End interrupt active high signal. This signal includes an internal pulldown and uses hysteresis.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
Table 4-2 DMD Control Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
DADOEZ AE7 VDD33 O5 Async DMD output-enable (active low). This signal does not apply to the secondary controller in a two-controller system configuration. On the secondary controller, this pin is reserved and Must be left unconnected
DADADDR_3
DADADDR_2
DADADDR_1
DADADDR_0		 AD6
AE5
AF4
AB8		 VDD33 O5 Async DMD address. This signal does not apply to the secondary controller in a two-controller system configuration. On the secondary controller, this pin is reserved and Must be left unconnected
DADMODE_1
DADMODE_0		 AD7
AE6		 VDD33 O5 Async DMD mode. This signal does not apply to the secondary controller in a two-controller system configuration. On the secondary controller, this pin is reserved and Must be left unconnected
DADSEL_1
DADSEL_0		 AE4
AC7		 VDD33 O5 Async DMD select. This signal does not apply to the secondary controller in a two-controller system configuration. On the secondary controller, this pin is reserved and Must be left unconnected
DADSTRB AF5 VDD33 O5 Async DMD strobe. This signal does not apply to the secondary controller in a two-controller system configuration. On the secondary controller, this pin is reserved and Must be left unconnected
DAD_INTZ AC8 VDD33 I4
H		 Async DMD interrupt (active low). Requires an external 1-kΩ pullup resistor.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
Table 4-3 DMD LVDS Interface Pin Functions
PIN(3)(4) I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
DCKA_P
DCKA_N		 V4
V3		 VDD18 O7 DCKA_P
DCKA_N		 DMD, LVDS interface channel A, differential clock.
SCA_P
SCA_N		 V2
V1		 VDD18 O7 DCKA_P
DCKA_N		 DMD, LVDS interface channel A, differential serial control.
DDA_P_15
DDA_N_15
DDA_P_14
DDA_N_14
DDA_P_13
DDA_N_13
DDA_P_12
DDA_N_12
DDA_P_11
DDA_N_11
DDA_P_10
DDA_N_10
DDA_P_9
DDA_N_9
DDA_P_8
DDA_N_8		 P4
P3
P2
P1
R4
R3
R2
R1
T4
T3
T2
T1
U4
U3
U2
U1		 VDD18 O7 DCKA_P
DCKA_N		 DMD, LVDS interface channel A, differential serial data.
DDA_P_7
DDA_N_7
DDA_P_6
DDA_N_6
DDA_P_5
DDA_N_5
DDA_P_4
DDA_N_4
DDA_P_3
DDA_N_3
DDA_P_2
DDA_N_2
DDA_P_1
DDA_N_1
DDA_P_0
DDA_N_0		 W4
W3
W2
W1
Y2
Y1
Y4
Y3
AA2
AA1
AA4
AA3
AB2
AB1
AC2
AC1
DCKB_P
DCKB_N		 J3
J4		 VDD18 O7 DCKB_P
DCKB_N		 DMD, LVDS interface channel B, differential clock.
SCB_P
SCB_N		 J1
J2		 VDD18 O7 DCKB_P
DCKB_N		 DMD, LVDS interface channel B, differential serial control.
DDB_P_15
DDB_N_15
DDB_P_14
DDB_N_14
DDB_P_13
DDB_N_13
DDB_P_12
DDB_N_12
DDB_P_11
DDB_N_11
DDB_P_10
DDB_N_10
DDB_P_9
DDB_N_9
DDB_P_8
DDB_N_8		 N1
N2
N3
N4
M2
M1
M3
M4
L1
L2
L3
L4
K1
K2
K3
K4		 VDD18 O7 DCKB_P
DCKB_N		 DMD, LVDS interface channel B, differential serial data.
DDB_P_7
DDB_N_7
DDB_P_6
DDB_N_6
DDB_P_5
DDB_N_5
DDB_P_4
DDB_N_4
DDB_P_3
DDB_N_3
DDB_P_2
DDB_N_2
DDB_P_1
DDB_N_1
DDB_P_0
DDB_N_0		 H1
H2
H3
H4
G1
G2
G3
G4
F1
F2
F3
F4
E1
E2
D1
D2
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) Several options allow reconfiguration of the DMD interface in order to better optimize board layout. The DLPC900 can swap channel A with channel B. The DLPC900 can also swap the data bit order within each channel independent of swapping the A and B channels.
(4) The DLPC900 is a full-bus DMD signaling interface. Figure 6-4 shows the controller connections for this configuration.
Table 4-4 Program Memory Flash Interface Pin Functions
PIN(3) I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION
NAME NUMBER CHIP SELECT 0
(ADDITIONAL FLASH)		 CHIP SELECT 1
(BOOT FLASH ONLY) (2)(3)		 CHIP SELECT 2
(ADDITIONAL FLASH)
PM_CSZ_0 (4) D13 VDD33 O5 Async Chip select
(active low)		 N/A N/A
PM_CSZ_1 (4) E12 VDD33 O5 Async N/A Boot flash chip select
(active low)		 N/A
PM_CSZ_2 (4) A13 VDD33 O5 Async N/A N/A Chip select
(active low)
PM_ADDR_22 (5) A12 VDD33 B5 Async Address bit (MSB) Address bit (MSB) Address bit (MSB)
PM_ADDR_21 (5) E11 VDD33 B5 Async Address bit Address bit Address bit
PM_ADDR_20 D12 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_19 C12 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_18 B11 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_17 A11 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_16 D11 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_15 C11 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_14 E10 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_13 D10 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_12 C10 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_11 B9 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_10 A9 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_9 E9 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_8 D9 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_7 C9 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_6 B8 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_5 A8 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_4 D8 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_3 C8 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_2 B7 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_1 A7 VDD33 O5 Async Address bit Address bit Address bit
PM_ADDR_0 C7 VDD33 O5 Async Address bit (LSB) Address bit (LSB) Address bit (LSB)
PM_WEZ B12 VDD33 O5 Async Write-enable
(active low)		 Write-enable
(active low)		 Write-enable
(active low)
PM_OEZ C13 VDD33 O5 Async Output-enable
(active low)		 Output-enable
(active low)		 Output-enable
(active low)
PM_BLSZ_1 B6 VDD33 O5 Async UpperByte(15:8) enable
(active low)		 N/A UpperByte(15:8) Enable
(active low)
PM_BLSZ_0 A6 VDD33 O5 Async LowerByte(7:0) enable
(active low)		 N/A LowerByte(7:0) Enable
(active low)
PM_DATA_15 C17 VDD33 B5 Async Data bit (15) Data bit (15) Data bit (15)
PM_DATA_14 B16 VDD33 B5 Async Data bit (14) Data bit (14) Data bit (14)
PM_DATA_13 A16 VDD33 B5 Async Data bit (13) Data bit (13) Data bit (13)
PM_DATA_12 A15 VDD33 B5 Async Data bit (12) Data bit (12) Data bit (12)
PM_DATA_11 B15 VDD33 B5 Async Data bit (11) Data bit (11) Data bit (11)
PM_DATA_10 D16 VDD33 B5 Async Data bit (10) Data bit (10) Data bit (10)
PM_DATA_9 C16 VDD33 B5 Async Data bit (9) Data bit (9) Data bit (9)
PM_DATA_8 E14 VDD33 B5 Async Data bit (8) Data bit (8) Data bit (8)
PM_DATA_7 D15 VDD33 B5 Async Data bit (7) Data bit (7) Data bit (7)
PM_DATA_6 C15 VDD33 B5 Async Data bit (6) Data bit (6) Data bit (6)
PM_DATA_5 B14 VDD33 B5 Async Data bit (5) Data bit (5) Data bit (5)
PM_DATA_4 A14 VDD33 B5 Async Data bit (4) Data bit (4) Data bit (4)
PM_DATA_3 E13 VDD33 B5 Async Data bit (3) Data bit (3) Data bit (3)
PM_DATA_2 D14 VDD33 B5 Async Data bit (2) Data bit (2) Data bit (2)
PM_DATA_1 C14 VDD33 B5 Async Data bit (1) Data bit (1) Data bit (1)
PM_DATA_0 B13 VDD33 B5 Async Data bit (0) Data bit (0) Data bit (0)
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) The default wait-state is set for a flash device of 120 ns access time. Therefore, the slowest flash access time supported is 120 ns. Refer to the Section 7.2.1.2.1.4.2 on how to program new wait-state values.
(3) Refer to the Figure 7-2 for the memory layout of the boot flash.
(4) Requires an external 10-kΩ pullup resistor.
(5) Requires an external 10-kΩ pulldown resistor.
Table 4-5 Port 1 and Port 2 Channel Data and Control Pin Functions
PIN (3) (4) (5) I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
P_CLK1 AE22 VDD33 I4
D		 N/A Input port data pixel write clock (selectable as rising or falling edge triggered, and with which port it is associated (Port 1 or Port 2 or (Port 1 and Port 2))).
P_CLK2 W25 VDD33 I4
D		 N/A Input port data pixel write clock (selectable as rising or falling edge triggered, and with which port it is associated (Port 1 or Port 2 or (Port 1 and Port 2))).
P_CLK3 AF23 VDD33 I4
D		 N/A Input port data pixel write clock (selectable as rising or falling edge triggered, and with which port it is associated (Port 1 or Port 2 or (Port 1 and Port 2))).
P_DATAEN1 AF22 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Active high data enable. Selectable as to which port it is associated with (Port 1 or Port 2 or (Port 1 and Port 2)).
P_DATAEN2 W24 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Active high data enable. Selectable as to which port it is associated with (Port 1 or Port 2 or (Port 1 and Port 2)).
P1_A9
P1_A8
P1_A7
P1_A6
P1_A5
P1_A4
P1_A3
P1_A2
P1_A1 (3)
P1_A0 (3)		 AD15
AE15
AE14
AE13
AD13
AC13
AF14
AF13
AF12
AE12		 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Port 1 A channel input pixel data (bit weight 128)
Port 1 A channel input pixel data (bit weight 64)
Port 1 A channel input pixel data (bit weight 32)
Port 1 A channel input pixel data (bit weight 16)
Port 1 A channel input pixel data (bit weight 8)
Port 1 A channel input pixel data (bit weight 4)
Port 1 A channel input pixel data (bit weight 2)
Port 1 A channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P1_B9
P1_B8
P1_B7
P1_B6
P1_B5
P1_B4
P1_B3
P1_B2
P1_B1 (3)
P1_B0 (3)		 AF18
AB18
AC15
AC16
AD16
AE16
AF16
AF15
AC14
AD14		 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Port 1 B channel input pixel data (bit weight 128)
Port 1 B channel input pixel data (bit weight 64)
Port 1 B channel input pixel data (bit weight 32)
Port 1 B channel input pixel data (bit weight 16)
Port 1 B channel input pixel data (bit weight 8)
Port 1 B channel input pixel data (bit weight 4)
Port 1 B channel input pixel data (bit weight 2)
Port 1 B channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P1_C9
P1_C8
P1_C7
P1_C6
P1_C5
P1_C4
P1_C3
P1_C2
P1_C1 (3)
P1_C0 (3)		 AD20
AE20
AE21
AF21
AD19
AE19
AF19
AF20
AC19
AE18		 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Port 1 C channel input pixel data (bit weight 128)
Port 1 C channel input pixel data (bit weight 64)
Port 1 C channel input pixel data (bit weight 32)
Port 1 C channel input pixel data (bit weight 16)
Port 1 C channel input pixel data (bit weight 8)
Port 1 C channel input pixel data (bit weight 4)
Port 1 C channel input pixel data (bit weight 2)
Port 1 C channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P1_VSYNC AC20 VDD33 B2
D		 P_CLK1, P_CLK2, or P_CLK3 Port 1 vertical sync. While intended to be associated with port 1, it can be programmed for use with port 2.
P1_HSYNC AD21 VDD33 B2
D		 P_CLK1, P_CLK2, or P_CLK3 Port 1 horizontal sync. While intended to be associated with port 1, it can be programmed for use with port 2.
P2_A9
P2_A8
P2_A7
P2_A6
P2_A5
P2_A4
P2_A3
P2_A2
P2_A1 (3)
P2_A0 (3)		 AD26
AD25
AB21
AC22
AD23
AB20
AC21
AD22
AE23
AB19		 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Port 2 A channel input pixel data (bit weight 128)
Port 2 A channel input pixel data (bit weight 64)
Port 2 A channel input pixel data (bit weight 32)
Port 2 A channel input pixel data (bit weight 16)
Port 2 A channel input pixel data (bit weight 8)
Port 2 A channel input pixel data (bit weight 4)
Port 2 A channel input pixel data (bit weight 2)
Port 2 A channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P2_B9
P2_B8
P2_B7
P2_B6
P2_B5
P2_B4
P2_B3
P2_B2
P2_B1 (3)
P2_B0 (3)		 Y22
AB26
AA23
AB25
AA22
AB24
AC26
AB23
AC25
AC24		 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Port 2 B channel input pixel data (bit weight 128)
Port 2 B channel input pixel data (bit weight 64)
Port 2 B channel input pixel data (bit weight 32)
Port 2 B channel input pixel data (bit weight 16)
Port 2 B channel input pixel data (bit weight 8)
Port 2 B channel input pixel data (bit weight 4)
Port 2 B channel input pixel data (bit weight 2)
Port 2 B channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P2_C9
P2_C8
P2_C7
P2_C6
P2_C5
P2_C4
P2_C3
P2_C2
P2_C1 (3)
P2_C0 (3)		 W23
V22
Y26
Y25
Y24
Y23
W22
AA26
AA25
AA24		 VDD33 I4
D		 P_CLK1, P_CLK2, or P_CLK3 Port 2 C channel input pixel data (bit weight 128)
Port 2 C channel input pixel data (bit weight 64)
Port 2 C channel input pixel data (bit weight 32)
Port 2 C channel input pixel data (bit weight 16)
Port 2 C channel input pixel data (bit weight 8)
Port 2 C channel input pixel data (bit weight 4)
Port 2 C channel input pixel data (bit weight 2)
Port 2 C channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P2_VSYNC U22 VDD33 B2
D		 P_CLK1, P_CLK2, or P_CLK3 Port 2 vertical sync. While intended to be associated with port 2, it can be programmed for use with port 1.
P2_HSYNC W26 VDD33 B2
D		 P_CLK1, P_CLK2, or P_CLK3 Port 2 horizontal sync. While intended to be associated with port 2, it can be programmed for use with port 1.
RESERVED_H23 H23 VDD33 B2 N/A Connects to BUS_SELECT signal on Primary Controller, must be left unconnected for Secondary Controller
RESERVED_G23 G23 VDD33 B2 N/A Connects to HDMI_CEC signal on Primary Controller, must be left unconnected for Secondary Controller
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) Port 1 and Port 2 are capable of 24-bits each. A maximum of 8-bits is available in each of the A, B, and C channels. The 8-bit color inputs are connected to bits [9:2] of the corresponding A, B, C input channels. Sources feeding 8-bits or less per color component channel are MSB justified when connected to the DLPC900, and the LSBs tied to ground along with the data lines 0 and 1 from every channel. Three port clocks options (1, 2, and 3) are provided to improve the signal integrity.
(4) Ports 1 and 2 can be used separately as two 24-bit ports, or can be combined into one 48-bit port (typically, for high data rate sources) for transmission of two pixels per clock.
(5) The A, B, C input data channels of ports 1 and 2 can be internally reconfigured or remapped for optimum board layout. Specifically each channel can individually remapped to the internal GBR channels. For example, G data can be connected to channel A, B, or C and remapped to be appropriate channel internally. Port configuration and channel multiplexing is handled in the API software.
Table 4-6 Clock and PLL Support Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
MOSC M26 VDD33 I10 N/A System clock oscillator input (3.3-V LVTTL). MOSC must be stable a maximum of 25 ms after POSENSE transitions from low to high.
MOSCN N26 VDD33 O10 N/A MOSC crystal return.
OCLKA (3) AF6 VDD33 O5 Async General-purpose output clock A. The frequency is software programmable. Power-up default is 787 kHz and the output frequency is maintained through all operations, except power loss and reset.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) This signal does not apply to the secondary controller in a two controller system configuration. On the secondary controller, this pin is reserved and Must be left unconnected Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
Table 4-7 Board-Level Test and Debug Pin Functions
PIN (3) I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
TDI N25 VDD33 I4
U		 TCK JTAG serial data in. Used in both Boundary Scan and ICE modes.
TCK N24 VDD33 I4
D		 N/A JTAG serial data clock. Used in both Boundary Scan and ICE modes.
TMS1 P25 VDD33 I4
U		 TCK JTAG test mode select. Used in Boundary Scan mode.
TMS2 P26 VDD33 I4
U		 TCK JTAG-ICE test mode select. Used in ICE mode.
TDO1 N23 VDD33 O5 TCK JTAG serial data out. Used in Boundary Scan mode.
TDO2 N22 VDD33 O5 TCK JTAG-ICE serial data out. Used in ICE mode.
TRSTZ M23 VDD33 I4
H
U		 Async JTAG Reset. Used in both Boundary Scan and ICE modes. This pin is pulled high (or left unconnected) when the JTAG interface is in use for boundary scan or debug. Connect this to ground otherwise. Failure to tie this pin low during standard operation will cause startup and initialization problems.
RTCK E4 VDD33 O2 N/A JTAG return clock. Used in ICE mode.
ICTSEN M24 VDD33 I4
H
D		 Async IC tri-state enable (active high). Asserting high will tri-state all outputs except the JTAG interface. Requires an external
4.7 kΩ pulldown resistor.
RESERVED_E8 E8 VDD33 B2
D		 N/A Connects to signal TSTPT7
RESERVED_B4 B4 VDD33 B2
D		 N/A Connects to signal TSTPT6
RESERVED_C4 C4 VDD33 B2
D		 N/A Connects to signal TSTPT5
RESERVED_E7 E7 VDD33 B2
D		 N/A Connects to signal TSTPT4
RESERVED_D5 D5 VDD33 B2
D		 N/A Connects to signal TSTPT3
RESERVED_E6 E6 VDD33 B2
D		 N/A Connects to signal TSTPT2
RESERVED_D3 D3 VDD33 B2
D		 N/A Connects to signal TSTPT1
RESERVED_C2 C2 VDD33 B2
D		 N/A Connects to signal TSTPT0
RESERVED_A4 A4 VDD33 B2
D		 N/A Connects to signal PIPESTAT2
RESERVED_B5 B5 VDD33 B2
D		 N/A Connects to signal PIPESTAT1
RESERVED_C6 C6 VDD33 B2
D		 N/A Connects to signal PIPESTAT0
RESERVED_A5 A5 VDD33 B2
D		 N/A Connects to signal TRACESYNC
RESERVED_D7 D7 VDD33 B2
D		 N/A Connects to signal TRACECLK
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) All JTAG signals are LVTTL compatible.
Table 4-8 Device Test Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
HW_TEST_EN M25 VDD33 I4
H
D		 N/A Device manufacturing test enable. This signal must be connected to an external ground for standard operation.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
Table 4-9 Peripheral Interface Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
I2C0_SCL A10 VDD33 B8 N/A I2C bus 0, clock. This bus supports 400 kHz, fast mode operation. This input is not 5 V tolerant. This pin requires an external pullup resistor to 3.3 V. The minimum acceptable pullup value is 1-kΩ resistor.
I2C0_SDA B10 VDD33 B8 I2C0_SCL I2C bus 0, data. This bus supports 400 kHz, fast mode operation. This input is not 5-V tolerant. This pin requires an external pullup resistor to 3.3 V. The minimum acceptable pullup value is 1-kΩ resistor.
I2C1_SDA (3) E19 VDD33 B2 I2C1_SCL I2C bus 1, data. This bus supports 400 kHz, fast mode operation. This input is not 5-V tolerant. This pin requires an external pullup resistor to 3.3 V. The minimum acceptable pullup value is 1-kΩ resistor.
I2C1_SCL (3) D20 VDD33 B2 N/A I2C bus 1, clock. This bus supports 400 kHz, fast mode operation. This input is not 5-V tolerant. This pin requires an external pullup resistor to 3.3 V. The minimum acceptable pullup value is 1-kΩ resistor.
I2C2_SDA (3) C21 VDD33 B2 I2C2_SCL I2C bus 2, data. This bus supports 400 kHz, fast mode operation. This input is not 5-V tolerant. This pin requires an external pullup resistor to 3.3 V. The minimum acceptable pullup value is 1-kΩ resistor.
I2C2_SCL (3) B22 VDD33 B2 N/A I2C bus 2, clock. This bus supports 400 kHz, fast mode operation. This input is not 5-V tolerant. This pin requires an external pullup resistor to 3.3 V. The minimum acceptable pullup value is 1-kΩ resistor.
RESERVED_AE8 AE8 VDD33 I4 N/A PMD Interrupt. This pin requires an external 10-kΩ pullup resistor.
RESERVED_AD8 AD8 VDD33 O5 N/A Color wheel control PWM output
SSP0_CLK AD4 VDD33 B5 N/A Synchronous serial port 0, clock
SSP0_RXD AD5 VDD33 I4 SSP0_CLK Synchronous serial port 0, receive data in
SSP0_TXD AB7 VDD33 O5 SSP0_CLK Synchronous serial port 0, transmit data out
SSP0_CSZ_0 (3) AC5 VDD33 B5 SSP0_CLK Synchronous serial port 0, chip select 0 (active low)
SSP0_CSZ_1 (3) AB6 VDD33 B5 SSP0_CLK Synchronous serial port 0, chip select 1 (active low)
This signal connects to the DMD SCP_ENZ input
SSP0_CSZ_2 (3) AC3 VDD33 B5 SSP0_CLK Synchronous serial port 0, chip select 2 (active low)
UART0_TXD AB3 VDD33 O5 Async UART0, UART transmit data output. The firmware only outputs debug messages on this port.
UART0_RXD AD1 VDD33 I4 Async UART0, UART receive data input. The firmware does not support receiving data on this port.
UART0_RTSZ AD2 VDD33 O5 Async UART0, UART ready to send hardware flow control output (active low)
UART0_CTSZ AE2 VDD33 I4 Async UART0, UART clear to send hardware flow control input (active low). This pin requires an external 10-kΩ pulldown resistor.
USB_DAT_N (3)
USB_DAT_P		 C5
D6		 VDD33 B9 Async USB D– I/O
USB D+ I/O
HOLD_BOOTZ F24 VDD33 B2 Async Boot mode. When this pin is held low, the firmware boots-up in bootload mode. When pin is held high, the firmware boots-up in default operating mode. This pin requires an external 1-kΩ pullup resistor.
USB_ENZ (3) E25 VDD33 B2 Async The firmware will use this pin to enable an external buffer on the USB data lines after it has completed initialization.
FAULT_STATUS AC11 VDD33 O2 Async This signal toggles or held high to indicate status faults. This pin requires an external 10-kΩ pulldown resistor.
HEARTBEAT AB12 VDD33 O2 Async This signal toggles to indicate the system is operational. Period is approximately 1 second.
RESERVED_AF8 AF8 VDD33 I4 N/A Lamp status pin. This pin requires an external 10-kΩ pulldown resistor.
SEQ_INT2 H26 VDD33 I2 Async This signal serves as an interrupt for pattern sequencing and must be connected to SEQ_AUX6.
SEQ_INT1 G26 VDD33 I2 Async This signal serves as an interrupt for pattern sequencing and must be connected to SEQ_AUX7.
SEQ_AUX7 F26 VDD33 O2 Async This signal serves as an interrupt for pattern sequencing and must be connected to SEQ_INT1.
SEQ_AUX6 E26 VDD33 O2 Async This signal serves as an interrupt for pattern sequencing and must be connected to SEQ_INT2.
TEST_FUNC_5 (3) K22 VDD33 B2 Async In a dual DLPC900 configuration, this pin connects to the FPGA and could serve as a configuration pin. Otherwise, this pin can be left unconnected.
TEST_FUNC_4 (3) J26 VDD33 B2 Async In a dual DLPC900 configuration, this pin connects to the FPGA and could serve as a configuration pin. Otherwise, this pin can be left unconnected.
TEST_FUNC_3 (3) J25 VDD33 B2 Async In a dual DLPC900 configuration, this pin connects to the FPGA and serves as a configuration pin. This function configures the 24-bit parallel data output of the FPGA to be split between the primary and the secondary controllers. The firmware will set this pin high by default.
TEST_FUNC_2 (3) J24 VDD33 B2 Async In a dual DLPC900 configuration, this pin connects to the FPGA and could serve as a configuration pin. Otherwise, this pin can be left unconnected.
TEST_FUNC_1 (3) J23 VDD33 B2 Async In a dual DLPC900 configuration, this pin connects to the FPGA and could serve as a configuration pin. Otherwise, this pin can be left unconnected.
GPIO_60 H22 VDD33 B2 N/A Used for Flash memory address extension ADDR_26. Pull down to GND with 10-kΩ resistor.
GPIO_46 T22 VDD33 B2 N/A Used for Flash memory address extension ADDR_25. Pull down to GND with 10-kΩ resistor.
GPIO_45 U23 VDD33 B2 N/A Used for Flash memory address extension ADDR_24. Pull down to GND with 10-kΩ resistor.
GPIO_08 (3) E21 VDD33 B2 Async This pin can be configured as GPIO 8. An external pullup resistor is required when this pin is configured as open-drain. (4)
GPIO_07 (3) V23 VDD33 B2 Async This pin can be configured as GPIO 7. An external pullup resistor is required when this pin is configured as open-drain.(4)
GPIO_06 (3) V24 VDD33 B2 Async This pin can be configured as GPIO 6. An external pullup resistor is required when this pin is configured as open-drain.(4)
GPIO_05 (3) U24 VDD33 B2 Async This pin can be configured as GPIO 5. An external pullup resistor is required when this pin is configured as open-drain.(4)
GPIO_04 (3) U25 VDD33 B2 Async This pin can be configured as GPIO 4. An external pullup resistor is required when this pin is configured as open-drain.(4)
GPIO_PWM_03 (3) A23 VDD33 B2 Async This pin can be configured as GPIO 3 or PWM 3. An external pullup resistor is required when this pin is configured as open-drain. (4)
GPIO_PWM_02 (3) A22 VDD33 B2 Async This pin can be configured as GPIO 2 or PWM 2. An external pullup resistor is required when this pin is configured as open-drain.(4)
GPIO_PWM_01 (3) B21 VDD33 B2 Async This pin can be configured as GPIO 1 or PWM 1. An external pullup resistor is required when this pin is configured as open-drain. (4)
GPIO_PWM_00 (3) A21 VDD33 B2 Async This pin can be configured as GPIO 0 or PWM 0. An external pullup resistor is required when this pin is configured as open-drain.(4)
RESERVED_AF9 AF9 VDD33 B2 N/A This pin connects to signal 3DLR_GPIO78
RESERVED_G24 G24 VDD33 B2 N/A This pin connects to signal IIC_BUSY (I2C_BUSY)
RESERVED_F23 F23 VDD33 B2 N/A This pin connects to signal SSP1_CSZ_1 of the primary controller in dual controller configuration. Otherwise leave unconnected.
RESERVED_D26 D26 VDD33 B2 N/A This pin connects to signal SSP1_CSZ_0 of the primary controller in dual controller configuration. Otherwise leave unconnected.
RESERVED_E24 E24 VDD33 B2 N/A This pin connects to signal SSP1_DO of the primary controller in dual controller configuration. Otherwise leave unconnected.
RESERVED_F22 F22 VDD33 B2 N/A This pin connects to signal SSP1_DIN of the primary controller in dual controller configuration. Otherwise leave unconnected.
RESERVED_D25 D25 VDD33 B2 N/A This pin connects to signal SSP1_CLK of the primary controller in dual controller configuration. Otherwise leave unconnected.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) This signal does not apply to the secondary controller in a two controller system configuration. On the secondary controller, this pin is reserved and Must be left unconnected Refer to Section 7.2.2 and Section 7.2.1 for a description between a one controller and a two controller configuration.
(4) GPIO signals must be configured through software for input, output, bidirectional, or open-drain. Some GPIO have one or more alternative use modes, which are also software-configurable. The reset default for all GPIO signals is as an input signal. Refer to the DLPC900 Programmer's Guide.
Table 4-10 Trigger Control Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
TRIG_IN_1(3) AF7 VDD33 I4 Async In video pattern mode, this signal is used for advancing the pattern display.
TRIG_IN_2(3) H25 VDD33 I2 Async In video pattern mode, the rising edge of this signal is used for starting the pattern display and the falling edge is used for stopping the pattern display. It works along with the software start stop command.
TRIG_OUT_1 E20 VDD33 O2 Async Active high trigger output signal during pattern exposure.
TRIG_OUT_2 D22 VDD33 O2 Async Active high trigger output to indicate first pattern display.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) These signals do not apply to the secondary controller in a two controller system configuration. On the secondary controller, these pins are reserved and are acceptable to be left unconnected. Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
Table 4-11 LED Control Pin Functions
PIN (3) I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
BLU_LED_PWM C20 VDD33 O2 Async Blue LED PWM current control signal.
GRN_LED_PWM B20 VDD33 O2 Async Green LED PWM current control signal.
RED_LED_PWM B19 VDD33 O2 Async Red LED PWM current control signal.
BLU_LED_EN D24 VDD33 O2 Async Blue LED enable signal.
GRN_LED_EN C25 VDD33 O2 Async Green LED enable signal.
RED_LED_EN B26 VDD33 O2 Async Red LED enable signal.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) These signals do not apply to the secondary controller in a two controller system configuration. On the secondary controller, these pins are reserved and Must be left unconnected Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
Table 4-12 Two Controller Support Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
SEQ_SYNC AB9 VDD33 B3 Async Sequence sync. This signal must be connected between the primary and secondary controller in a two controller configuration. Do not leave unconnected. This pin requires an external 10-kΩ pullup resistor.
SSP0_CSZ4_SLV U26 VDD33 B2 SSP0_CLK This signal is used by the primary controller to communicate with the secondary controller over the SSP interface. This pin requires an external 4.7-kΩ pullup resistor.
FSD12_OUTPUT T23 VDD33 B2 Async This pin must be connected to DA_SYNC_INPUT (3).
DA_SYNC_INPUT R22 VDD33 B2 Async This pin must be connected to FSD12_OUTPUT (4).
SLV_CTRL_PRST V25 VDD33 B2 Async This signal must be connected between the primary and secondary controller in a two controller configuration. The secondary controller will pull this signal high to inform the primary controller that it is present and ready. This pin requires an external 10-kΩ pulldown resistor. Do not leave unconnected.
CTRL_MODE_CFG V26 VDD33 B2 Async When this pin is high, the controller operates as the primary controller. When this pin is low the controller operates as the secondary controller. Use an external 4.7-kΩ pullup or pulldown resistor to identify the controller. Do not leave unconnected.
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) The FSD12_OUTPUT of the secondary controller Must be left unconnected
(4) The DA_SYNC_INPUT of the secondary controller must be connected to the FSD12_OUTPUT of the primary controller.
Table 4-13 Reserved Pin Functions
PIN I/O POWER I/O TYPE(1) CLK SYSTEM DESCRIPTION(2)
NAME NUMBER
RESERVED_AD12 AD12 VDD33 O6 N/A Reserved. Must be left unconnected
RESERVED_AF11 AF11 VDD33 I4 N/A Reserved. Must be left unconnected
RESERVED_AD11 AD11 VDD33 I4 N/A Reserved. Must be left unconnected
RESERVED_AE11 AE11 VDD33 I4 N/A Reserved. Must be left unconnected
RESERVED_AC9 AC9 VDD33 O5 N/A Reserved. Must be left unconnected
RESERVED_E3 E3 VDD33 B5 N/A Reserved. Must be left unconnected
RESERVED_AB10 AB10 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AD9 AD9 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AE9 AE9 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AB11 AB11 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AC10 AC10 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AD10 AD10 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AE10 AE10 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AF10 AF10 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_K24 K24 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_K23 K23 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_J22 J22 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_H24 H24 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_G25 G25 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_F25 F25 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_G22 G22 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_E23 E23 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_C26 C26 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_AB4 AB4 VDD33 B5 N/A Reserved. Must be left unconnected
RESERVED_C23 C23 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_D21 D21 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_B24 B24 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_C22 C22 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_B23 B23 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_A20 A20 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_A19 A19 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_E18 E18 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_D19 D19 VDD33 B2 N/A Reserved. Must be left unconnected
RESERVED_C19 C19 VDD33 B2 N/A Reserved. Must be left unconnected
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
Table 4-14 Power and Ground Pin Functions
PIN(3) I/O TYPE(1) DESCRIPTION(2)
NAME NUMBER
VDD33 F20, F17, F11, F8, L21, R21, Y21, PWR 3.3-V I/O power
AA19, AA16, AA10, AA7
VDD18 C1, F5, G6, K6, M5, P5, T5, PWR 1.8-V internal DRAMVDD and LVDSAVD I/O power
(To shut this power down in a system low-power mode, see the Section 8.3.)
W6, AA5, AE1, H5, N6, T6,
AA13, U21, P21, H21, F14
VDDC F19, F16, F13, F10, F7, H6, L6, PWR 1.15-V core power
P6, U6, Y6, AA8, AA11, AA14, AA17,
AA20, W21, T21, N21, K21, G21, L11,
T11, T16, L16
PLLD_VDD L22 PWR 1.15-V DMD clock generator PLL
Digital power
PLLD_VSS L23 GND 1.15-V DMD clock generator PLL
Digital GND
PLLD_VAD K25 PWR 1.8-V DMD clock generator PLL
Analog power
PLLD_VAS K26 GND 1.8-V DMD clock generator PLL
Analog GND
PLLM1_VDD L26 PWR 1.15-V primary-LS clock generator PLL
Digital power
PLLM1_VSS M22 GND 1.15-V primary-LS clock generator PLL
Digital GND
PLLM1_VAD L24 PWR 1.8-V primary-LS clock generator PLL
Analog power
PLLM1_VAS L25 GND 1.8-V primary-LS clock generator PLL
Analog GND
PLLM2_VDD P23 PWR 1.15-V primary-HS clock generator PLL
Digital power
PLLM2_VSS P24 GND 1.15-V primary-HS clock generator PLL
Digital GND
PLLM2_VAD R25 PWR 1.8-V primary-HS clock generator PLL
Analog power
PLLM2_VAS R26 GND 1.8-V primary-HS clock generator PLL
Analog GND
PLLS_VAD R23 PWR 1.15-V video-2X clock generator PLL
Analog power
PLLS_VAS R24 GND 1.15-V video-2X clock generator PLL
Analog GND
L_VDQPAD_[7:0], R_VDQPAD_[7:0] B18, D18, B17, E17, A18, C18, A17, RES DRAM direct test pins (for manufacturing use only). These pins must be tied directly to ground when in operation.
D17, AE17, AC17, AF17, AC18, AB16, AD17,
AB17, AD18
CFO_VDD33 AE26 RES DRAM direct test control pin (for manufacturing use only). This pin must be tied directly to 3.3 I/O power (VDD33) when in operation.
VTEST1, VTEST2, VTEST3, VTEST4 AB14, AB15, E15, E16 RES DRAM direct test control pins (for manufacturing use only).  These pins must be tied directly to ground when in operation.
LVDS_AVS1, LVDS_AVS2 V5, K5 PWR Dedicated ground for LVDS bandgap reference. These pins must be tied directly to ground when in operation.
VPGM AC6 PWR Fuse programming pin (for manufacturing use only). This pin must be tied directly to ground when in operation.
GND A26, A25, A24, B25, C24, D23, GND Common ground
E22, F21, F18, F15, F12, F9, F6,
E5, D4, C3, B3, A3, B2, A2,
B1, A1, G5, J5, J6, L5, M6,
N5, R5, R6, U5, V6, W5, Y5,
AA6, AB5, AC4, AD3, AE3, AF3, AF2,
AF1, AA9, AA12, AA15, AA18, AA21, AB22,
AC23, AD24, AE24, AF24, AE25, AF25, AF26,
V21, M21, J21, L15, L14, L13, L12,
M16, M15, M14, M13, M12, M11, N16,
N15, N14, N13, N12, N11, P16, P15,
P14, P13, P12, P11, R16, R15, R14,
R13, R12, R11, T15, T14, T13, T12
Table 4-15 I/O Type and Subscript Definition
I/O ESD STRUCTURE
(SUBSCRIPT)(3) DESCRIPTION
1 N/A N/A
2 3.3 LVTTL I/O buffer, with 8-mA drive ESD diode to VDD33 and GND
3 3.3 LVTTL I/O buffer, with 12-mA drive
4 3.3 LVTTL receiver
5 3.3 LVTTL I/O buffer, with 8-mA drive, with slew rate control
6 3.3 LVTTL I/O buffer, with programmable 4-, 8-, or 12-mA drive
7 1.8-V LVDS (DMD interface)
8 3.3-V I2C with 3-mA sink
9 USB-compatible (3.3 V)
10 OSC 3.3-V I/O compatible LVTTL
(TYPE) N/A
I Input
O Output
B Bidirectional
H Hysteresis
U Includes an internal termination pullup resistor
D Includes an internal termination pulldown resistor
(1) Refer to I/O Type and Subscript Definition (Table 4-15).
(2) Refer to the Section 7.2.2 and the Section 7.2.1 for a description between a one controller and a two controller configuration.
(3) Refer to the Section 9.1.7 for instructions on handling unused pins.