DLPS037G October   2014  – November 2023 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics #GUID-A1639D57-2918-4D83-ADD0-B21B369F4B9B/DLPS0379327
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15-V System Power
        2. 8.1.1.2 1.8-V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5-V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER (1)TEST CONDITIONS (4)MINTYPMAXUNIT
VIHHigh-level input threshold voltageUSB (9)2V
OSC (10)2
3.3-V LVTTL (1, 2, 3, 4)2
3.3-V I2C (8)2.4VDD33 + 0.5
VILLow-level input threshold voltageUSB (9)0.8V
OSC (10)0.8
3.3-V LVTTL (1, 2, 3, 4)0.8
3.3-V I2C (8)–0.51
VDISDifferential input sensitivity
(Differential input voltage)		USB (9)200 mV
VICMInput common mode range
(Differential cross point voltage)		USB (9)0.82.5 V
VOHHigh-level output voltageUSB (9)2.8V
1.8-V LVDS (7)1.52
3.3-V LVTTL (1, 2, 3)IOH = Max rated2.7
VOLLow-level output voltageUSB (9)00.3V
1.8-V LVDS (7)0.88
3.3-V LVTTL (1, 2, 3)IOL = Max rated0.4
3.3-V I2C (8)IOL = 3-mA sink0.4
VODOutput differential voltage1.8-V LVDS (7)0.0650.44V
IIHHigh-level input currentUSB (9)200µA
OSC (10)–1010
3.3-V LVTTL (1 to 4) (without internal pulldown)VIH = VDD33–1010
3.3-V LVTTL (1 to 4) (with internal pulldown)VIH = VDD3310200
3.3-V I2C (8)VIH = VDD3310
IILLow-level input currentUSB (9)–1010µA
OSC (10)–1010
3.3-V LVTTL (1-4) (without internal pullup)VOH = VDD33–1010
3.3-V LVTTL (1-4) (with internal pullup)VOH = VDD33–10–200
3.3-V I2C (8)VOH = VDD33–10
IOHHigh-level output current (2)USB (9)–18.4mA
1.8-V LVDS (7)
(VOD = 300 mV)		VO = 1.4 V–6.5
3.3-V LVTTL (1)VO = 2.4 V–4
3.3-V LVTTL (2)VO = 2.4 V–8
3.3-V LVTTL (3)VO = 2.4 V–12
IOLLow-level output current (3)USB (9)19.1mA
1.8-V LVDS (7)
(VOD = 300 mV)		VO = 1 V6.5
3.3-V LVTTL (1)VO = 0.4 V4
3.3-V LVTTL (2)VO = 0.4 V8
3.3-V LVTTL (3)VO = 0.4 V12
3.3-V I2C (8)3
IOZHigh-impedance leakage currentUSB (9)–1010 µA
LVDS (7)–1010
3.3-V LVTTL (1, 2, 3)–1010 
3.3-V I2C (8)–1010
CIInput capacitance (including package)USB (9)11.8417.07pF
3.3-V LVTTL (1)3.755.52
3.3-V LVTTL (2)3.755.52
3.3-V LVTTL (4)3.755.52
3.3-V I2C (8)5.266.54
ICC11Supply voltage, 1.15-V core powerNormal mode2368mA
ICC18Supply voltage, 1.8-V power (LVDS I/O and internal DRAM)Normal mode1005mA
ICC33Supply voltage, 3.3-V I/O powerNormal mode33mA
ICC11_PLLDSupply voltage, DMD PLL digital power (1.15 V)Normal mode4.46.2mA
ICC11_PLLM1Supply voltage, primary-LS clock generator PLL digital power (1.15 V)Normal mode4.46.2mA
ICC11_PLLM2Supply voltage, primary-HS clock generator PLL digital power (1.15 V)Normal mode4.46.2mA
ICC18_PLLDSupply voltage, DMD PLL analog power (1.8 V)Normal mode810.2mA
ICC18_PLLM1Supply voltage, primary-LS clock generator PLL analog power (1.8 V)Normal mode810.2mA
ICC18_PLLM2Supply voltage, primary-HS clock generator PLL analog power (1.8 V)Normal mode810.2mA
ICC11_PLLSSupply voltage, video-2X PLL analog power
(1.15 V)		Normal mode2.9mA
Total Power in Normal Mode4.76W
(1) The number inside the parentheses for the I/O refers to the I/O type defined in Table 4-15.
(2) VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT – VDDQ) / IOH must be < 21 Ω for values of VOUT between VDDQ and VDDQ – 280 mV.
(3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be < 21 Ω for values of VOUT between 0 V and 280 mV.
(4) Normal mode refers to DLPC900 operation during full functionality. Typical values correspond to power dissipated on nominal process devices operating at nominal voltage and 70°C junction temperature (approximately 25°C ambient) displaying typical video-graphics content from a high-frequency source. Max values correspond to power dissipated on fast-process devices operating at high voltage and 105°C junction temperature (approximately 55°C ambient) displaying typical video-graphics content from a high-frequency source. The increased power dissipation observed on fast-process devices operated at max recommended temperature is primarily a result of increased leakage current.