Immediately after any type of system reset (power-up reset, PWRGOOD reset, watchdog timer time-out, and so forth), the DLPC900 automatically returns to normal power mode and returns to the following state:
- All GPIO will tri-state.
- The primary PLL will remain active (it is only
reset on a power-up reset) and most of the derived clocks will be active.
However, only those resets associated with the DLPC900 processor and its
peripherals will be released. (The DLPC900 firmware is responsible for releasing
all other resets).
- The DLPC900 associated clocks will default to their full clock rates (boot-up is at full speed).
- The PLL feeding the LVDS DMD interface (PLLD) will default to its power-down mode and all derived clocks will be inactive with corresponding resets asserted. (The DLPC900 firmware is responsible for enabling these clocks and releasing associated resets).
- LVDS I/O will default to its power-down mode with tri-stated outputs.
- All resets output by the DLPC900 will remain asserted until released by the firmware (after boot-up).
- The DLPC900 processor will boot-up from external flash.
Once the DLPC900 processor boots-up, the DLPC900 firmware will:
- Configure the programmable DDR clock generator (DCG) clock rates (that is, the DMD LVDS interface rate)
- Enable the DCG PLL (PLLD) while holding divider logic in reset
- After the DCG PLL locks, the processor software will set DMD clock rates
- API software will then release DCG divider logic resets, which in turn, will enable all derived DCG clocks
- Release external resets
The LVDS I/O is reset by a system reset event and remains in reset until released by the DLPC900 firmware. Thus, the software is responsible for waiting until power is restored to these components before releasing reset.