DLPS037F October 2014 – June 2021 DLPC900
All applications require both the controller and DMD components for reliable operation. The system uses an external parallel flash memory device loaded with the DLPC900 configuration and support firmware. The external boot flash must contain a minimum of 2 sectors, where the first sector starts at address 0xF9000000 which is the power-up reset start address. The first 128-kilobytes is reserved for the bootloader image and must be in its own sector and can be made up of several smaller contiguous sectors that add up to 128-kilobytes as shown in Figure 8-2. The remaining sectors contains the rest of the firmware. The default wait-states is set for a flash device of 120-ns access time. For a faster flash access time, refer to the Section 22.214.171.124.1.4.2 on how to program new wait-state values.
The bootloader, the main application, and any images stored in flash (if present) are considered the firmware.
The chipset has the following interfaces and support circuitry: