SLVSHO1 March   2025 TPS1689

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  PMBus and GPIO DC Characteristics
    7. 5.7  Telemetry
    8. 5.8  Logic Interface
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Protection
      2. 6.3.2  Insertion Delay
      3. 6.3.3  Overvoltage Protection
      4. 6.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 6.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 6.3.4.1.1 Start-Up Timeout
        2. 6.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 6.3.4.3 Active Current Limiting During Start-Up
        4. 6.3.4.4 Short-Circuit Protection
      5. 6.3.5  Analog Load Current Monitor (IMON)
      6. 6.3.6  Overtemperature Protection
      7. 6.3.7  Analog Junction Temperature Monitor (TEMP)
      8. 6.3.8  FET Health Monitoring
      9. 6.3.9  Single Point Failure Mitigation
        1. 6.3.9.1 IMON Pin Single Point Failure
        2. 6.3.9.2 IREF Pin Single Point Failure
      10. 6.3.10 General Purpose Digital Input/Output Pins
        1. 6.3.10.1 Fault Response and Indication (FLT)
        2. 6.3.10.2 Power Good Indication (PG)
        3. 6.3.10.3 Parallel Device Synchronization (SWEN)
      11. 6.3.11 Stacking Multiple eFuses for Unlimited Scalability
        1. 6.3.11.1 Current Balancing During Start-Up
      12. 6.3.12 Quick Output Discharge(QOD)
      13. 6.3.13 Write Protect Feature(WP#)
      14. 6.3.14 PMBus® Digital Interface
        1. 6.3.14.1  PMBus® Device Addressing
        2. 6.3.14.2  SMBus Protocol
        3. 6.3.14.3  SMBus™ Message Formats
        4. 6.3.14.4  Packet Error Checking
        5. 6.3.14.5  Group Commands
        6. 6.3.14.6  SMBus™ Alert Response Address (ARA)
        7. 6.3.14.7  PMBus® Commands
        8. 6.3.14.8  Analog-to-digital Converter
        9. 6.3.14.9  Digital-to-analog Converters
        10. 6.3.14.10 DIRECT format Conversion
        11. 6.3.14.11 Blackbox Fault Recording
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single Device, Standalone Operation
      2. 7.1.2 Single TPS1689 and multiple TPS1685 Devices, Parallel Connection
      3. 7.1.3 Multiple TPS1689 Devices: Parallel Connection With Individual Telemetry
      4. 7.1.4 Multiple Devices, Independent Operation (Multi-zone)
    2. 7.2 Typical Application: 54-V, 2-kW Power Path Protection with PMBus® Interface in Datacenter Servers
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Performance Plots
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Transient Protection
      2. 7.3.2 Output Short-Circuit Measurements
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Application Limitation and Errata
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.14.8 Analog-to-digital Converter

The TPS1689 integrates a 10-bit, 460 KSPS SAR ADC preceded by an analog MUX. The following signals are available for sampling by the ADC:

  1. VIN

  2. VOUT

  3. VIMON

  4. VTEMP

  5. VAUX

  6. ADDR0

  7. ADDR1

The ADC uses a 5kHz low-pass filter at the input to suppress high frequency noise (outside the ADC Nyquist bandwidth) and prevent aliasing.

Note:

The ADC also supports a high performance mode wherein the sampling rate is traded off in favor of improved DNL and INL. In this mode, the sampling rate is reduced to 270 KSPS. This mode can be selected by setting the ADC_HI_PERF bit in the DEVICE_CONFIG register.

During normal operation, the ADC automatically sequences the channels. The ADC channel sequencer manages MUX channel selection for sampling.

Note:

  • The ADDR0 and ADDR1 signals are sampled only at startup to decode the PMBus® target address.

  • The ADC implements background self-calibration to eliminate offset and gain errors inherent to the ADC.

The device also supports buffering of multiple samples of a selected parameter in RAM, which can be read by the host using the ADC_SAMPLE_BUF block read command. This allows the system designer to reconstruct the time domain profile/waveform of that parameter in a given interval. This can be useful during design/debugging by functioning like an in-built "digital oscilloscope". The ADC channel to sample for buffering and the decimation rate/sample skip count can be user configured using PMBus® writes to the ADC_CONFIG_2 register.

The TPS1689 can post-process raw ADC sampled data to compute the following derived parameters:

  1. VIN Average

  2. VIN Peak

  3. VIN Min

  4. VOUT Average

  5. VOUT Min

  6. IIN Average

  7. IIN Peak

  8. PIN

  9. PIN Average

  10. PIN Peak

  11. EIN

  12. Temperature Average

  13. Temperature Peak

A single ADC sample can have higher errors due to internal noise. It’s possible to improve the ADC SNR and the telemetry accuracy by averaging higher number of samples. The number of samples to be averaged is user-programmable using the PK_MIN_AVG register. The minimum, maximum, and average values can also be reset using the PK_MIN_AVG register.

The TPS1689 performs digital comparison on the ADC sampled data to detect the following system events.

  1. VIN UV WARN

  2. VIN UV FAULT

  3. VIN OV WARN

  4. VOUT PGOOD

  5. IIN OC WARN

  6. OT WARN

  7. OT FAULT

  8. PIN OP WARN

The results of the comparisons are reflected in the PMBus® status registers and can be configured to trigger other actions e.g. FET turn OFF (protection response) and FLT output assertion for faults, SMBA# signal assertion for faults/warnings and Blackbox RAM/EEPROM update.