SLVSHO1 March   2025 TPS1689

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  PMBus and GPIO DC Characteristics
    7. 5.7  Telemetry
    8. 5.8  Logic Interface
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Protection
      2. 6.3.2  Insertion Delay
      3. 6.3.3  Overvoltage Protection
      4. 6.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 6.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 6.3.4.1.1 Start-Up Timeout
        2. 6.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 6.3.4.3 Active Current Limiting During Start-Up
        4. 6.3.4.4 Short-Circuit Protection
      5. 6.3.5  Analog Load Current Monitor (IMON)
      6. 6.3.6  Overtemperature Protection
      7. 6.3.7  Analog Junction Temperature Monitor (TEMP)
      8. 6.3.8  FET Health Monitoring
      9. 6.3.9  Single Point Failure Mitigation
        1. 6.3.9.1 IMON Pin Single Point Failure
        2. 6.3.9.2 IREF Pin Single Point Failure
      10. 6.3.10 General Purpose Digital Input/Output Pins
        1. 6.3.10.1 Fault Response and Indication (FLT)
        2. 6.3.10.2 Power Good Indication (PG)
        3. 6.3.10.3 Parallel Device Synchronization (SWEN)
      11. 6.3.11 Stacking Multiple eFuses for Unlimited Scalability
        1. 6.3.11.1 Current Balancing During Start-Up
      12. 6.3.12 Quick Output Discharge(QOD)
      13. 6.3.13 Write Protect Feature(WP#)
      14. 6.3.14 PMBus® Digital Interface
        1. 6.3.14.1  PMBus® Device Addressing
        2. 6.3.14.2  SMBus Protocol
        3. 6.3.14.3  SMBus™ Message Formats
        4. 6.3.14.4  Packet Error Checking
        5. 6.3.14.5  Group Commands
        6. 6.3.14.6  SMBus™ Alert Response Address (ARA)
        7. 6.3.14.7  PMBus® Commands
        8. 6.3.14.8  Analog-to-digital Converter
        9. 6.3.14.9  Digital-to-analog Converters
        10. 6.3.14.10 DIRECT format Conversion
        11. 6.3.14.11 Blackbox Fault Recording
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single Device, Standalone Operation
      2. 7.1.2 Single TPS1689 and multiple TPS1685 Devices, Parallel Connection
      3. 7.1.3 Multiple TPS1689 Devices: Parallel Connection With Individual Telemetry
      4. 7.1.4 Multiple Devices, Independent Operation (Multi-zone)
    2. 7.2 Typical Application: 54-V, 2-kW Power Path Protection with PMBus® Interface in Datacenter Servers
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Performance Plots
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Transient Protection
      2. 7.3.2 Output Short-Circuit Measurements
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Application Limitation and Errata
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.10.3 Parallel Device Synchronization (SWEN)

The SWEN pin is a signal which is driven high when the FET needs to be driven to ON state. When it is driven low (internally or externally), it forces the driver circuit to keep the FET in OFF condition. In a parallel eFuse system, this pin is used by the TPS1689 primary controller to control the other eFuses. It also allows multiple devices in a parallel configuration to synchronize the ON/OFF transitions.

Table 6-4 SWEN Summary

Device State

FET Driver Status

SWEN

Steady-state

ON

H

Inrush

ON

H

Overtemperature shutdown

OFF

L

Auto-retry timer running

OFF

L

Device disabled ( VEN < VUVLO)

OFF

L

VIN Undervoltage (VIN < VUVP or VIN < VIN_UV_FLT)

OFF

L

VDD Undervoltage (VDD < VUVP)

OFF

L

Insertion delay

OFF

L

VIN Overvoltage (VIN > VIN_OV_FLT)

OFF

L

Transient overcurrent

ON

H

Circuit-breaker (persistent overcurrent followed by OC_TIMER expiry)

OFF

L

Fast-trip

OFF

L

Fast-trip response mono-shot running (DEVICE_CONFIG[13] = 1)

OFF

L

Fast-trip response mono-shot expired (DEVICE_CONFIG[13] = 1)

ON

H

FET health fault

OFF

L

External fault (SWEN pulled low by secondary device in parallel chain)

OFF

L (held low by TPS1689 even if secondary device releases the pull down after some time)
Single Point Failure(IMON/IREF) OFF L

The SWEN is an open-drain pin and has an internal pull-up to internal power supply.

The SWEN pin has an internal timeout circuit. If the SWEN is held low (internally or externally) for an extended period of time (tSWENTO), it resets the logic (FAST_REC = 0) so that the next time the device starts up after SWEN goes high, it follows the normal inrush sequence. In other cases, it may bypass the inrush sequence and perform a current limited startup for fast recovery.

In a primary and secondary parallel configuration, the SWEN pin is used by the primary device to control the ON and OFF transitions of the secondary devices. At the same time, it allows the secondary devices to communicate any faults or other conditions which can prevent it from turning on the primary device.

To maintain state machine synchronization, the devices rely on SWEN level transitions as well as timing for handshakes. This ensures all the devices turn ON and OFF synchronously and in the same manner (for example, dVdt controlled or current limited start-up). There are also fail-safe mechanisms in the SWEN control and handshake logic to ensure the entire chain is turned off safely even if the primary device is unable to take control in case of a fault.

Note:

TI recommends to keep the parasitic loading on the SWEN pin to a minimum to avoid synchronization timing issues.