SLVSHO1 March   2025 TPS1689

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  PMBus and GPIO DC Characteristics
    7. 5.7  Telemetry
    8. 5.8  Logic Interface
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Protection
      2. 6.3.2  Insertion Delay
      3. 6.3.3  Overvoltage Protection
      4. 6.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 6.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 6.3.4.1.1 Start-Up Timeout
        2. 6.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 6.3.4.3 Active Current Limiting During Start-Up
        4. 6.3.4.4 Short-Circuit Protection
      5. 6.3.5  Analog Load Current Monitor (IMON)
      6. 6.3.6  Overtemperature Protection
      7. 6.3.7  Analog Junction Temperature Monitor (TEMP)
      8. 6.3.8  FET Health Monitoring
      9. 6.3.9  Single Point Failure Mitigation
        1. 6.3.9.1 IMON Pin Single Point Failure
        2. 6.3.9.2 IREF Pin Single Point Failure
      10. 6.3.10 General Purpose Digital Input/Output Pins
        1. 6.3.10.1 Fault Response and Indication (FLT)
        2. 6.3.10.2 Power Good Indication (PG)
        3. 6.3.10.3 Parallel Device Synchronization (SWEN)
      11. 6.3.11 Stacking Multiple eFuses for Unlimited Scalability
        1. 6.3.11.1 Current Balancing During Start-Up
      12. 6.3.12 Quick Output Discharge(QOD)
      13. 6.3.13 Write Protect Feature(WP#)
      14. 6.3.14 PMBus® Digital Interface
        1. 6.3.14.1  PMBus® Device Addressing
        2. 6.3.14.2  SMBus Protocol
        3. 6.3.14.3  SMBus™ Message Formats
        4. 6.3.14.4  Packet Error Checking
        5. 6.3.14.5  Group Commands
        6. 6.3.14.6  SMBus™ Alert Response Address (ARA)
        7. 6.3.14.7  PMBus® Commands
        8. 6.3.14.8  Analog-to-digital Converter
        9. 6.3.14.9  Digital-to-analog Converters
        10. 6.3.14.10 DIRECT format Conversion
        11. 6.3.14.11 Blackbox Fault Recording
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single Device, Standalone Operation
      2. 7.1.2 Single TPS1689 and multiple TPS1685 Devices, Parallel Connection
      3. 7.1.3 Multiple TPS1689 Devices: Parallel Connection With Individual Telemetry
      4. 7.1.4 Multiple Devices, Independent Operation (Multi-zone)
    2. 7.2 Typical Application: 54-V, 2-kW Power Path Protection with PMBus® Interface in Datacenter Servers
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Performance Plots
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Transient Protection
      2. 7.3.2 Output Short-Circuit Measurements
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Application Limitation and Errata
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)

The TPS1689 responds to output overcurrent conditions during steady-state by performing a circuit-breaker action after a user-adjustable transient fault blanking interval. This action allows the device to support a higher peak current for a short user-defined interval but also ensures robust protection in case of persistent output faults.

The device constantly senses the output load current and provides an analog current output (IIMON) on the IMON pin which is proportional to the load current, which in turn produces a proportional voltage (VIMON) across the IMON pin resistor (RIMON) as per Equation 4.

Equation 4. V I M O N = I O U T × G I M O N × R I M O N

Where GIMON is the current monitor gain (IIMON : IOUT)

The overcurrent condition is detected by comparing this voltage against the voltage on the IREF pin as a reference. The reference voltage (VIREF) can be controlled in two ways, which sets the overcurrent protection threshold (IOCP) accordingly.

  • The reference voltage (VIREF) can be generated using internal DAC and can be changed by programming the non-volatile configuration memory or dynamically through PMBus® writes to the VIREF register.

  • It is also possible to drive the IREF pin from an external low impedance precision reference voltage source.

The overcurrent protection threshold during steady-state (IOCP) can be calculated using Equation 5.

Equation 5. I O C P = V I R E F G I M O N × R I M O N
Note:

TI recommends to add a 1 nF capacitor from IREF pin to GND for improved noise immunity.

After an overcurrent condition is detected, that is the load current exceeds the programmed current limit threshold (IOCP), but stays lower than the short-circuit threshold (ISCP), the device starts running the internal overcurrent blanking digital timer (OC_TIMER). If the load current drops below the current limit threshold before the OC_TIMER expires, the circuit-breaker action is not engaged. This action allows short overload transient pulses to pass through the device without tripping the circuit. At the same time, the OC_TIMER is reset so that it is at its default state before the next overcurrent event. This ensures the full blanking timer interval is provided for every overcurrent event.

If the overcurrent condition persists, the OC_TIMER continues to run and after it expires, the circuit-breaker action turns off the FET immediately.

Equation 15 can be used to calculate the RIMON value for the desired overcurrent threshold.

Equation 6. R I M O N = V I R E F G I M O N × I O C P

The duration for which transients are allowed can be programmed using OC_TIMER register setting through PMBus® writes.

Figure 6-4 illustrates the overcurrent response for TPS1689 eFuse. After the part shuts down due to a circuit-breaker fault, it either stays latched off or restarts automatically based on the RETRY_CONFIG register setting.

TPS1689 Steady-state Overcurrent (Circuit-Breaker) ResponseFigure 6-4 Steady-state Overcurrent (Circuit-Breaker) Response

When a transient overcurrent condition (the load current exceeds the programmed current limit threshold but the OC_TIMER does not expire) is detected, the device:

  • sets the OC_DET bit in the STATUS_MFR_SPECIFIC_2 register

  • fills-up one of the Blackbox RAM registers (if available to write) writing the event identifier as OC_DET and relative time stamp information

  • increases the Blackbox RAM address pointer in the BB_TIMER register by one (1) if it was previously less than six (6), otherwise resets to zero (0).

Note:

It is assumed that the VIN_UV_WARN , VIN_OV_WARN, and VOUT_UV_WARN events are not triggered because of a step load transient.

When a persistent overcurrent condition (the load current exceeds the programmed current limit threshold and the OC_TIMER expires) is detected, the device:

  • sets the FET_OFF and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register

  • sets the OUT_STATUS, INPUT_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the STATUS_WORD register

  • sets the VOUT_UV_WARN bit in the STATUS_OUT register

  • sets the OC_FLT bit in the STATUS_INPUT register

  • sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

  • notifies the host by asserting SMBA, if it is not masked setting the STATUS_IN, PGOODB, and STATUS_OUT bits in the ALERT_MASK register.

  • deasserts the external PG signal.

  • asserts the FLT signal, if it is not masked setting the OC_FLT bit high in the FAULT_MASK register.

Note:

It is assumed that the VIN_UV_WARN and VIN_OV_WARN events are not triggered because of a step load transient.