SLVSHO1 March   2025 TPS1689

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  PMBus and GPIO DC Characteristics
    7. 5.7  Telemetry
    8. 5.8  Logic Interface
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Protection
      2. 6.3.2  Insertion Delay
      3. 6.3.3  Overvoltage Protection
      4. 6.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 6.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 6.3.4.1.1 Start-Up Timeout
        2. 6.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 6.3.4.3 Active Current Limiting During Start-Up
        4. 6.3.4.4 Short-Circuit Protection
      5. 6.3.5  Analog Load Current Monitor (IMON)
      6. 6.3.6  Overtemperature Protection
      7. 6.3.7  Analog Junction Temperature Monitor (TEMP)
      8. 6.3.8  FET Health Monitoring
      9. 6.3.9  Single Point Failure Mitigation
        1. 6.3.9.1 IMON Pin Single Point Failure
        2. 6.3.9.2 IREF Pin Single Point Failure
      10. 6.3.10 General Purpose Digital Input/Output Pins
        1. 6.3.10.1 Fault Response and Indication (FLT)
        2. 6.3.10.2 Power Good Indication (PG)
        3. 6.3.10.3 Parallel Device Synchronization (SWEN)
      11. 6.3.11 Stacking Multiple eFuses for Unlimited Scalability
        1. 6.3.11.1 Current Balancing During Start-Up
      12. 6.3.12 Quick Output Discharge(QOD)
      13. 6.3.13 Write Protect Feature(WP#)
      14. 6.3.14 PMBus® Digital Interface
        1. 6.3.14.1  PMBus® Device Addressing
        2. 6.3.14.2  SMBus Protocol
        3. 6.3.14.3  SMBus™ Message Formats
        4. 6.3.14.4  Packet Error Checking
        5. 6.3.14.5  Group Commands
        6. 6.3.14.6  SMBus™ Alert Response Address (ARA)
        7. 6.3.14.7  PMBus® Commands
        8. 6.3.14.8  Analog-to-digital Converter
        9. 6.3.14.9  Digital-to-analog Converters
        10. 6.3.14.10 DIRECT format Conversion
        11. 6.3.14.11 Blackbox Fault Recording
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single Device, Standalone Operation
      2. 7.1.2 Single TPS1689 and multiple TPS1685 Devices, Parallel Connection
      3. 7.1.3 Multiple TPS1689 Devices: Parallel Connection With Individual Telemetry
      4. 7.1.4 Multiple Devices, Independent Operation (Multi-zone)
    2. 7.2 Typical Application: 54-V, 2-kW Power Path Protection with PMBus® Interface in Datacenter Servers
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Performance Plots
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Transient Protection
      2. 7.3.2 Output Short-Circuit Measurements
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Application Limitation and Errata
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.10.1 Fault Response and Indication (FLT)

Table 6-2 summarizes the device response to various fault conditions.

Table 6-2 Fault Summary

Event or Condition

Device Response

Fault Latched Internally

FLT Pin StatusPin Indication Masking Option

Delay

Steady-state

None

N/A

H

N/A

Inrush

None

N/A

H

N/A

Overtemperature

Shutdown

Y

L

Y

Undervoltage (EN/UVLO)

Shutdown

N

H

N/A

Undervoltage (VDD UVP)

Shutdown

N

H

N/A

Undervoltage (VIN UVP)

Shutdown

N

H

N/A

Overvoltage (VIN OVP)

Shutdown

N

H

N/A

Transient overcurrent

None

N

H

N/A

Persistent overcurrent (steady-state)

Circuit-Breaker

Y

L

Y

tITIMER

Persistent overcurrent (start-up)

Current Limit

N

H

N/A

Post TSD

Output short-circuit

Fast-trip

Y

L

Y

tFT

Output short-circuit (Fast recovery configuration)

Fast-trip followed by current limited Start-up

N

H

N/A

IMON pin open (steady-state)

Shutdown

Y

L

Y

IMON pin short (steady-state)

Shutdown (If IOUT > IOC_BKP)

Y

L

Y

45μs

IREF pin open (start-up)

Shutdown (If IOUT > IOC_BKP)

Y

L

Y

IREF pin open (steady-state)

Shutdown (if IOUT > IOC_BKP)

Y

L

Y

tITIMER

IREF pin short (steady-state)

Shutdown

Y

L

Y

IREF pin short (start-up)

Shutdown

Y

L

Y

Start-up timeout

Shutdown

Y

L

N

tSU_TMR

FET health fault (G-S)

Shutdown

Y

L

Y

10μs

FET health fault (G-D)

Shutdown

Y

L

Y

FET health fault (D-S)

Shutdown

N

L

Y

tSU_TMR

External fault (SWEN pulled low externally while device is not in UV or OV)

Shutdown

Y

L

Y

The device response after a fault varies based on the RETRY_CONFIG register setting. The device latches a fault as per the table above and thereafter follows an auto-retry or latch-off response. For auto-retry configuration, the latched faults also trigger the start of the Auto-Retry Timer, while keeping the FLT pin pulled low. On expiry of the timer period (tRETRY), the FLT pin pull-down is released and the device is ready to restart automatically. When the device turns on again, it follows the usual DVDT limited start-up sequence.

The only exception to this is during Short-circuit fault when the device is configured for fast recovery using the SC_RETRY bit in the DEVICE_CONFIG register. In this case, the device turns off quickly and then automatically turns back on in a current limited manner. This allows the system to try and recover quickly from any transient faults. See Short-Circuit Protection section for more details.

For faults that are latched internally, power cycling the part or pulling the EN/UVLO pin voltage below VSD(F) clears the fault and the FLT pin is de-asserted. This action also clears the Auto-retry timer. Pulling the EN/UVLO just below the UVLO threshold has no impact on the device in this condition. This is true in case of latch-off and auto-retry configurations.

In a parallel eFuse configuration involving TPS1689 and TPS1685x, the fault response is determined by the TPS1689 as the primary device. However, if the primary device fails to register a fault, there is a fail-safe mechanism in the secondary device to take control and turn off the entire chain by pulling the SWEN pin low and enter a latch-off condition. Thereafter, the device can be turned on again only by power cycling VDD below VUVP(F) or by cycling EN/UVLO pin below VSD(F).