SLLSFZ7 February   2025 TUSB1146-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.2
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration In I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Linear EQ Configuration
      5. 6.4.5 Linearity VOD
      6. 6.4.6 VOD Modes
        1. 6.4.6.1 Linearity VOD
        2. 6.4.6.2 Limited VOD
      7. 6.4.7 Transmit Equalization
      8. 6.4.8 USB3.2 Modes
      9. 6.4.9 Downstream Facing Port Adaptive Equalization
        1. 6.4.9.1 Fast Adaptive Equalization in I2C Mode
        2. 6.4.9.2 Full Adaptive Equalization
        3. 6.4.9.3 Full Adaptive Equalization in GPIO Mode (I2C_EN = "F")
    5. 6.5 Programming
      1. 6.5.1 Transition Between Modes
      2. 6.5.2 Pseudocode Examples
        1. 6.5.2.1 Fast AEQ With Linear Redriver Mode
        2. 6.5.2.2 Fast AEQ With Limited Redriver Mode
        3. 6.5.2.3 Full AEQ With Linear Redriver Mode
        4. 6.5.2.4 Full AEQ With Limited Redriver Mode
      3. 6.5.3 TUSB1146-Q1 I2C Address Options
      4. 6.5.4 TUSB1146-Q1 I2C Target Behavior
  9. Register Maps
    1. 7.1 TUSB1146-Q1 Registers
  10. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C Receptacle) Configuration
        2. 8.2.2.2 USB Downstream Facing Port (USB-C Receptacle to USB Host) Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Fast Adaptive Equalization
          3. 8.2.2.2.3 Full Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2-Lane DisplayPort Mode
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Linear EQ Configuration

Each of the TUSB1146-Q1 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 6-7 details the gain value for each available combination when the TUSB1146-Q1 is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL.

Table 6-7 USB Downstream Facing Port Receiver (RX1 and RX2 Pins) Equalization Control
Register(s): EQ1_SEL or EQ2_SEL
Equalization Setting #
EQ1 PIN LevelEQ0 PIN LevelEQ Gain at 2.5GHz / 5.0GHz minus Gain at 100MHz
(dB)
000-1.0/-0.4
10R0.0/1.8
20F0.9/3.2
3011.8/4.6
4R02.6/5.5
5RR3.4/6.5
6RF4.0/7.2
7R14.6/7.8
8F05.2/8.3
9FR5.7/8.9
10FF6.1/9,2
11F16.5/9.5
12106.8/9.7
131R7.1/10.0
141F7.5/10.2
15117.8/10.4
Table 6-8 USB Upstream Facing Port Receiver (SSTX Pins) Equalization Control
Register(s): SSEQ_SEL
Equalization Setting #
SSEQ1 PIN LEVELSSEQ0 PIN LEVELEQ Gain at 2.5GHz / 5.0GHz minus Gain at 100MHz
(dB)
000-0.5/0.1
10R0.6/2.2
20F1.5/3.7
3012.5/5.1
4R03.2/6.0
5RR4.0/7.0
6RF4.6/7.6
7R15.2/8.3
8F05.7/8.8
9FR6.3/9.3
10FF6.6/9.6
11F17.1/10.0
12107.4/10.2
131R7.8/10.5
141F8.0/10.7
15118.4/10.9
Table 6-9 DisplayPort Receiver (DP[3:0] Pins) Equalization Control
Register(s): DP0EQ_SEL, DP1EQ_SEL,
DP2EQ_SEL, or DP3EQ_SEL
Equalization Setting #
DPEQ1 PIN LEVELDPEQ0 PIN LEVELEQ Gain at 2.7/4.05/5GHz minus Gain at 100MHz
(dB)
0000.4/0.8/0.83
10R2.0/3.1/3.4
20F3.0/4.6/5.0
3014.2/6.0/6.5
4R05.0/7.0/7.5
5RR6.0/8.0/8.4
6RF6.5/8.7/9.1
7R17.2/9.4/9.8
8F07.8/10.0/10.3
9FR8.3/10.4/10.7
10FF8.7/10.7/10.9
11F19.1/11.1/11.2
12109.4/11.3/11.3
131R9.7/11.5/11.5
141F10.0/11.7/11.6
151110.2/11.8/11.7